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Published in 1987, SAE J1567 (also known as J1567) defines a serial data communications bus and bus interface IC intended for distributed processing vehicle multiplex systems. Rather than adopting classic collision-detection methods (CSMA/CD) with nondeterministic random backoff, this standard specifies a deterministic priority access method using non-destructive bit-by-bit arbitration. The protocol is built around a simple message format—SOM, identifier bytes, data, and EOM—with idle periods permitted between bytes to simplify firmware control and direct connection to a host microcontroller’s asynchronous serial port. Byte synchronization NRZ (non-return-to-zero) encoding was chosen over PWM and Bi-Phase for its superior noise immunity, higher data rates, and lower EMI. The system is broadcast-oriented, so nodes can be added or removed with minimal impact.
The engineering society for advancing mobility, SAE, issued this Information Report to provide a simple, reliable data communications link among members of a distributed processing vehicle multiplex system. The protocol minimizes the software overhead required of modules on the multiplex bus. The network access method selected is CSMA (Carrier Sense Multiple Access) with a deterministic priority arbitration scheme—non-destructive bit-by-bit arbitration—instead of the nondeterministic random backoff procedure associated with classic collision detection. This ensures that the highest priority message always wins bus access without wasting time on collisions. The message format supports a number of higher-level protocols and allows idle periods between each byte, enabling firmware control and direct connection to the host microcontroller’s asynchronous serial I/O port.
The message structure consists of a start-of-message (SOM) byte, one or two identifier bytes (ID1, ID2) that uniquely define message content in a broadcast system, data bytes (any form: values, CRC, checksum, length, acknowledgment, etc.), and an end-of-message (EOM) byte. The identifier bytes also carry the arbitration priority; during the ID field, multiple transmitters contend and the one with the highest-priority ID continues without data loss.
| Bit Encoding Method | Noise Tolerance | Relative Data Rate | EMI Generation | Clock Precision Need |
|---|---|---|---|---|
| NRZ (byte sync) | Up to 50% of samples can be corrupted before data loss | Highest | Low | Moderate (crystal or ceramic resonator already available) |
| PWM | Significantly smaller, duty-cycle dependent | Lower | Higher | Low |
| Bi-Phase | Similar to PWM | Lower | Higher | Low |
Byte sync NRZ was selected because it provides the best compromise between bandwidth efficiency and data recovery in a noisy vehicle environment while maintaining required high network data rates. Empirical data indicated NRZ could operate at significantly higher bit rates than PWM or Bi-Phase without generating excessive EMI. Although NRZ demands a more precise clock than self-clocking schemes, all module applications already demanded a crystal or ceramic resonator, so this was not a disadvantage.
Design Insight – By using CSMA with deterministic priority access (bit-by-bit arbitration) instead of random backoff, the standard ensures deterministic latency for high-priority messages. This decision is crucial for real-time vehicle control systems where timing predictability matters more than statistical throughput.
The choice of broadcast topology with unique message identifiers enables easy addition or removal of nodes without network reconfiguration. The collision detection hardware within the interface IC determines which transmitting ID wins without losing bus time when contention occurs. This hardware arbitration satisfies the need for establishing access priority and gaining control of latency for important messages. The message format and data integrity method are firmware-determined, giving maximum flexibility for future applications.
Common Mistake – Assuming that “collision detection” implies a random backoff scheme like IEEE 802.3 CSMA/CD. SAE J1567 uses non-destructive bit-by-bit arbitration, where the highest-priority message wins immediately without retransmission or lost bandwidth. The ID field in the message is a unique content identifier (not a source/destination address), broadcast to all nodes.
Q1: How does non-destructive bit-by-bit arbitration work?
During the ID field, all contending transmitters drive the bus simultaneously. Each bit is a wired-AND; if a node tries to send a recessive bit (e.g., logic 1) but sees a dominant bit (logic 0) on the bus, it loses arbitration and stops transmitting. The node sending the dominant bit continues because its bit matches the bus. This ensures the message with the highest-priority (lowest numeric ID) wins without any data destruction.
Q2: Why are idle periods allowed between bytes?
Idle periods simplify the controller firmware and allow direct connection to the microcontroller’s asynchronous serial port. The bus does not require strict back-to-back byte transmission; gaps are permitted as part of the protocol. This reduces hardware complexity and makes it easier to implement the interface with standard UARTs.
Q3: What clock accuracy is needed for byte sync NRZ encoding?
NRZ relies on precise bit timing because there is no embedded clock. The standard assumes modules use a crystal or ceramic resonator (already required for other functions) which provides sufficient precision. Typical tolerances of ±0.5% to ±1% are acceptable for the data rates and bus lengths envisioned.
Q4: Is the network addressed or broadcast?
It is a broadcast system. Each message carries a unique identifier that describes the content of the data, not the intended recipient. Every node receives all messages and filters based on the identifier. This allows easy addition of nodes that recognize existing identifiers without changing the network configuration.