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ISO/IEC 29167-21 specifies the use of Advanced Encryption Standard (AES) in Galois/Counter Mode (GCM) as a cryptographic suite for RFID systems. AES-GCM is an authenticated encryption (AE) algorithm that provides both confidentiality (encryption) and integrity (authentication) in a single unified operation. For RFID applications, this dual property is particularly valuable because it eliminates the need for separate encryption and MAC engines, reducing both gate count and protocol overhead.
The standard defines two modes of operation: AES-GCM for full authenticated encryption and AES-GMAC (Galois Message Authentication Code) for authentication-only scenarios. Both modes support 128-bit keys as the minimum requirement, with optional support for 192-bit and 256-bit keys. The underlying AES core operates on 128-bit data blocks with the GCM mode producing ciphertext of equal length to the plaintext plus a 32-128 bit authentication tag.
The AES-GCM protocol in ISO/IEC 29167-21 begins with the reader sending an initialization vector (IV, 96 bits recommended) to the tag. The tag increments a 32-bit counter starting from the IV to generate unique counter blocks for each plaintext block. Each counter block is encrypted with AES-128, and the result is XOR-ed with the corresponding plaintext block to produce ciphertext. Simultaneously, the ciphertext blocks are multiplied in GF(2^128) to compute the GMAC authentication tag.
One critical advantage of GCM over other modes (such as CCM used in 29167-11) is that the AES encryption and the GHASH computation can be pipelined: while the AES core encrypts block N+1, the GF multiplier computes the authentication tag for block N. This pipelining allows GCM to achieve throughput close to the raw AES encryption rate with minimal additional latency.
| Parameter | AES-128-GCM | AES-192-GCM | AES-256-GCM |
|---|---|---|---|
| Key Size | 128 bits | 192 bits | 256 bits |
| IV / Nonce Size | 96 bits | 96 bits | 96 bits |
| Auth Tag Size | 32-128 bits | 32-128 bits | 32-128 bits |
| Gate Count (est.) | ~10,000 GE | ~12,000 GE | ~15,000 GE |
| Throughput @ 1 MHz | ~8 Mbps | ~6.5 Mbps | ~5 Mbps |
| AAD Support | Yes | Yes | Yes |
Implementing AES-GCM in an RFID tag requires two main hardware blocks: an AES-128 encryption core and a GF(2^128) multiplier for GHASH. The AES core represents approximately 70% of the total gate count and the GF multiplier about 25%, with control logic making up the remainder. For tags requiring only authentication (not encryption), the GMAC-only mode eliminates the need for output ciphertext buffering, reducing the gate count by approximately 15%.
Power management is a key concern for passive tags using AES-GCM. A full AES-128 encryption round consumes approximately 5-10 microjoules in a typical 130 nm CMOS process. For passive tags operating at typical read ranges (2-5 meters from a 4W ERP reader), the available power is approximately 10-50 microwatts. This means that an AES-GCM operation requiring 50-100 clock cycles at 1.6 MHz will take 30-60 microseconds and consume a significant fraction of the available energy budget. Designers must carefully sequence the AES-GCM operations with power harvesting and storage to prevent brown-out during cryptographic processing.