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ISO/IEC 29167-13 specifies the Grain-128A stream cipher as a cryptographic suite for RFID security services. Grain-128A is an evolution of the eSTREAM finalist Grain v1, designed by Hell, Johansson, and Meier. It is a lightweight stream cipher that uses an 128-bit key and a 96-bit initialization vector (IV) to generate a keystream for encrypting data. Unlike block ciphers such as AES-128 and PRESENT-80, which operate on fixed-size blocks, Grain-128A generates a continuous keystream that can be XORed with data of arbitrary length — a natural fit for RFID applications where message sizes vary from a few bytes (authentication tokens) to hundreds of bytes (user data reads).
The cipher is built around two shift registers: a 128-bit Linear Feedback Shift Register (LFSR) and a 128-bit Nonlinear Feedback Shift Register (NFSR). The LFSR ensures a long period and good statistical properties, while the NFSR introduces nonlinearity that resists algebraic and correlation attacks. The output function combines bits from both registers through a nonlinear Boolean function to produce the keystream bit. During the initialization phase, the key and IV are loaded into the registers, and the cipher is clocked 256 times without producing output, allowing the state to mix thoroughly.
The standard defines Grain-128A’s operation within the SMP framework for two primary functions: (1) encrypted data transfer using the generated keystream, and (2) message authentication using a ciphertext feedback mode. For encryption, the reader and tag first synchronize their cipher states by exchanging an IV through the Authenticate command. Once synchronized, both parties generate identical keystreams and use them to encrypt and decrypt subsequent messages.
| Phase | Operation | Data Flow | Clock Cycles Required |
|---|---|---|---|
| 1. IV Exchange | Reader sends 96-bit IV | Reader → Tag | — (over-the-air) |
| 2. Initialization | Load key + IV, 256 clocks | Internal (tag) | 256 @ 100 kHz = 2.56 ms |
| 3. Keystream Generation | Generate N bits | Internal (both) | N @ 1 bit/clock |
| 4. Data XOR | Encrypt/decrypt payload | Bidirectional | — (combinatorial) |
The message authentication mode uses a ciphertext feedback approach. After encrypting the message, the tag computes an authentication tag by feeding the ciphertext back into the cipher state for an additional 64 clock cycles. The resulting 64-bit MAC is appended to the encrypted message. The reader performs the same computation to verify the MAC. This integrated authenticated encryption (AE) scheme eliminates the need for a separate MAC engine, reducing the overall gate count by approximately 15% compared to implementing encryption and authentication separately.
Grain-128A provides 128-bit security against brute-force key search. The cipher has been extensively analyzed since its introduction, and as of 2026, the best known attacks are against reduced-round variants only. The full 256-clock initialization provides strong resistance against related-key attacks and time-memory-data tradeoff attacks. The 128-bit internal state size limits the keystream length to 2^64 bits before the LFSR state repeats, which is far beyond any practical RFID usage scenario.
Hardware implementation of Grain-128A on an RFID tag is relatively straightforward. The two 128-bit shift registers require 256 flip-flops, and the nonlinear feedback and output functions require approximately 800 gates of combinatorial logic. The total area of 2,130 GE makes it an attractive middle ground between the ultra-compact PRESENT-80 and the more capable AES-128. Power consumption at 100 kHz is approximately 2.5 µW in a 0.18 µm process, well within the tag’s power budget. For initialization, the tag needs to draw power continuously for 2.56 ms — a duration that the reader can support by maintaining a continuous carrier wave during the computation period.