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IEC TS 62910:2015 provides a standardized test procedure for verifying the low voltage ride-through (LVRT) capability of utility-interconnected photovoltaic inverters. As grid codes worldwide increasingly mandate fault ride-through for distributed generation, this technical specification fills a critical gap by defining reproducible test methods that manufacturers, testing laboratories, and grid operators can rely on for type approval and commissioning verification.
The standard defines three distinct test circuit topologies for generating controlled voltage sags. The choice of topology depends on the available test equipment and the type of sag to be simulated.
| Topology | Sag Types Generated | Equipment Required | Advantages |
|---|---|---|---|
| Three-phase short-circuit | Symmetrical three-phase sag (Type A) | Three single-phase switches + reactor bank | Simple, repeatable sag depths |
| Two-phase (phase-to-phase) short-circuit | Phase-to-phase sag (Type C) | Two switches + phase reactor | Tests unbalanced fault response |
| Single-phase short-circuit with/without ground | Phase-to-ground sag (Type B) | Single switch + resistor/reactor | Most common fault type in distribution networks |
The test circuit must be connected between the grid simulator (or low-voltage grid) and the inverter under test. A series impedance (typically 0.1-5 Ω per phase) limits the fault current during the sag. The standard requires that the sag be initiated within one-half cycle of the grid frequency and maintained with a steady-state accuracy of ±2% in magnitude.
The core of LVRT testing is the voltage tolerance curve, which defines the minimum voltage magnitude that the inverter must withstand as a function of fault duration. The standard provides generic curves adaptable to national grid code requirements.
For the generic test profile, the inverter must remain connected for voltage sags as low as 15% of nominal voltage retained for up to 500 ms. For sags remaining above 80% retained voltage, the inverter shall stay connected indefinitely without tripping. The transition between the “must-ride-through” region and the “may-trip” region follows a linear slope on the log-time scale.
| Retained Voltage (% V_nom) | Required Ride-Through Duration (s) | Active Power Recovery | Reactive Current Injection |
|---|---|---|---|
| 15% ≤ V < 30% | 0.15 | N/A (priority to reactive) | 100% reactive current |
| 30% ≤ V < 50% | 0.50 | N/A (priority to reactive) | 100% reactive current |
| 50% ≤ V < 80% | 1.00 | Linear recovery starting at sag clearance | Proportional to voltage drop |
| 80% ≤ V ≤ 90% | 3.00 | Full recovery within 1 s | Optional |
| V ≥ 90% | Continuous | Normal operation | Not required |
After fault clearance, the inverter must ramp active power back to at least 80% of pre-fault output within 1 second and reach 100% within 5 seconds. The standard permits a 100 ms delay after voltage recovery before the ramp begins, allowing the phase-locked loop to re-synchronize. Measurement accuracy for power recovery tracking shall be within ±2% of full scale.
The complete test sequence comprises 24 individual sag events across the three topologies at different retained voltage levels and durations. For each test point, the inverter passes if it: (a) remains connected to the grid throughout the sag, (b) injects the required reactive current within 40 ms of sag onset, (c) does not exceed 110% of rated current during the fault, and (d) recovers active power within the specified time window.
The standard also requires three repeat tests at each operating point to account for statistical variation. If any single test fails, an investigation into the root cause is mandatory before retesting.