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IEC TR 62834:2013 is a Technical Report prepared by IEC TC 113 (Nanotechnology for electrical and electronic products). It establishes a standardization roadmap for nanomaterials and nanoscale devices covering electronics and ICT applications. The roadmap uses a Gantt chart format showing standardization priorities and timelines from 2009 to 2020.
The background section classifies nanotechnology into nanomaterials, nanoscale devices, nano-biotechnology, and nanofabrication processes. For the first version, the ICT ‘More Moore’ area was prioritized to achieve consensus more quickly, focusing on electronics applications where the TC 113 expert base is strongest.
Clause 4 presents detailed standardization scenarios for various nanomaterials. Zero-dimensional: Nanoparticles and quantum dots require standards for particle size distribution, shape, surface area, chemical composition, and purity. One-dimensional: Carbon nanotubes (CNT) and nanowires need standardized measurement of aspect ratio, chirality, electrical properties, and dispersion quality. Two-dimensional: Nanostructured thin films and graphene require standards for layer number determination, sheet resistance, and defect density. Three-dimensional: Nanopores and nanocomposites need characterization of pore size distribution, filler dispersion, and mechanical properties.
Notably, the roadmap identifies sheet resistance characterization of CNT films, wear resistance testing, and thermal characterization as priority standardization items with direct industrial relevance.
Clause 5 addresses nanoelectronic devices including non-volatile memory devices (flash, FeRAM, MRAM, PRAM), 3D nanoscale transistors (FinFET, gate-all-around), single electron transistors (SET), nanoscale logic devices, carbon interconnects, nanoscale magnetic devices, and molecular devices.
The roadmap prioritizes nanoscale non-volatile memory devices as the highest priority due to their near-term market impact. Three-dimensional nanoscale transistors follow closely, driven by the semiconductor industry’s roadmap beyond 22 nm nodes. Carbon nanotube interconnects and single electron transistors are positioned for medium-term standardization as the technologies mature. This TR has been influential in guiding the work of TC 113 and related standards development organizations.
| Category | Examples | Priority Items | Timeline |
|---|---|---|---|
| 0D Nanomaterials | Nanoparticles, Quantum dots | Size distribution, purity, surface chemistry | 2009-2015 |
| 1D Nanomaterials | Carbon nanotubes, Nanowires | Aspect ratio, electrical properties, chirality | 2010-2017 |
| 2D Nanomaterials | Graphene, Thin films | Layer count, sheet resistance, defects | 2012-2018 |
| 3D Nanomaterials | Nanopores, Nanocomposites | Pore size, filler dispersion, mechanical | 2013-2020 |
| Nanoelectronic devices | NVM, 3D transistors, SET, molecular | Memory, logic, interconnects | 2009-2020 |
It provides a standardization roadmap identifying priority areas for nanoelectronics standardization from 2009 to 2020. It helps standards development organizations and industry plan their standardization activities for nanomaterials and nanoscale devices.
Carbon nanotubes and nanoparticles received the earliest priority due to their advanced commercialization status. Graphene standardization was identified as a priority from 2012 onward as production methods matured.
Nanoscale non-volatile memory devices and 3D transistors (FinFET, gate-all-around) were prioritized highest due to their near-term market impact in the semiconductor industry beyond the 22 nm node.