IEC TR 62543: HVDC — Modular Multilevel Converters

IEC TR 62543, published in 2017 as a Technical Report by IEC Technical Committee 22 (Power Electronic Systems and Equipment), provides a comprehensive technical description of modular multilevel converters (MMCs) for high-voltage direct current (HVDC) transmission applications. As the global deployment of VSC-HVDC systems accelerates — driven by offshore wind farm integration, cross-border grid interconnection, and long-distance bulk power transmission — understanding MMC technology has become essential for power electronics engineers, transmission planners, and utility technical specialists.

The MMC topology, first patented in 2001 and commercially deployed since 2010, has rapidly become the dominant voltage-source converter (VSC) topology for HVDC applications above 100 MW. Its advantages over conventional two-level and three-level VSC topologies include lower harmonic distortion (eliminating or greatly reducing the need for AC filters), higher efficiency (typically 98-99% including transformers), modularity enabling voltage scaling to any desired level without series-connected valves, and inherent redundancy through additional submodules. These characteristics have made MMC the technology of choice for nearly all VSC-HVDC projects commissioned since 2014, with total installed capacity exceeding 30 GW worldwide by 2025.

MMC Topology and Operating Principles

The fundamental MMC structure consists of three phase legs, each containing two arms — an upper arm and a lower arm. Each arm comprises a series connection of N nominally identical submodules (SMs) and an arm inductor L_arm. The submodules are the basic building blocks of the MMC, each capable of being switched into (inserted) or bypassed from the arm current path, thereby contributing to the synthesized AC voltage waveform. The arm inductor serves multiple functions: limiting circulating currents between phases, suppressing fault current rise rates, and filtering the switching-frequency ripple in the arm currents.

The standard defines the fundamental relationships governing MMC operation. The output voltage per phase is the difference between the upper and lower arm voltages, each of which is modulated around the DC voltage midpoint. A critical design parameter is the ratio of the AC voltage amplitude to the DC voltage, known as the modulation index, typically maintained between 0.85 and 1.0 for optimal utilization of the DC bus voltage. The arm currents contain both an AC component (half the phase current) and a DC component (one-third of the DC link current, plus circulating current components). The second-harmonic circulating current, which flows between phases without appearing in the AC or DC terminals, must be actively suppressed to reduce submodule capacitor voltage ripple and minimize converter losses.

Modulation and Control Strategies

IEC TR 62543 describes the two principal modulation methods used in MMC systems. Nearest Level Modulation (NLM) is favored for high-voltage applications with large numbers of submodules (typically N > 50 per arm), where the AC voltage waveform can be synthesized with sufficient accuracy by selecting the nearest discrete voltage level at each switching instant. NLM naturally produces very low harmonic distortion (THD typically below 0.5%) and achieves low switching frequencies per submodule (typically 100-200 Hz average), contributing to high converter efficiency. For medium-voltage applications or MMCs with fewer submodules, Phase-Shifted Carrier Pulse Width Modulation (PSC-PWM) may be used, where each submodule is modulated with an interleaved triangular carrier signal, producing an effective switching frequency that is N times the individual carrier frequency.

The control system architecture for MMC-HVDC is organized hierarchically. At the highest level, the system control determines the active power (or DC voltage) and reactive power (or AC voltage) references based on grid operator requirements. The converter control level implements vector current control in a synchronous reference frame (d-q coordinates), generating the AC voltage magnitude and phase angle references for the phase legs. The arm-balancing control distributes the arm voltages between upper and lower arms, and the submodule-level control performs capacitor voltage balancing within each arm, ensuring that the N submodule capacitor voltages remain within a defined tolerance band (typically ±5% of the nominal voltage). The standard emphasizes that the circulating current suppression controller (CCSC), typically implemented using a resonant controller tuned to twice the fundamental frequency, is essential for reducing submodule capacitor voltage ripple and improving overall converter efficiency by 0.2-0.5 percentage points.

A distinctive feature of MMC control addressed in IEC TR 62543 is the energy balance control between the upper and lower arms. Under unbalanced AC grid conditions, the positive and negative sequence currents interact with the arm voltages to produce power pulsations at twice the fundamental frequency. These pulsations, if not properly controlled, can lead to excessive voltage ripple in the submodule capacitors and potentially trigger overvoltage protection. The standard describes control strategies for handling unbalanced faults, including negative sequence current injection limits, arm energy balancing using zero-sequence voltage injection, and the use of second-harmonic circulating current components to compensate for the energy imbalance. For systems connected to weak AC grids (short-circuit ratio SCR below 2.5), additional control complexity is required to maintain stable operation, including phase-locked loop (PLL) optimization and power-synchronization control.

Engineering Design Insights for MMC-HVDC Systems

From a practical engineering perspective, several critical design considerations emerge from IEC TR 62543. First, the submodule capacitor voltage ripple is a fundamental constraint that drives both the capacitor sizing and the control strategy. The capacitor voltage ripple is inversely proportional to the submodule capacitance and the fundamental frequency, and proportional to the arm current magnitude. For 50/60 Hz systems, a typical ripple specification of ±10% at rated power leads to an energy storage requirement of 30-50 kJ/MVA. For low-frequency applications such as motor drives or low-speed pumped hydro starting, the capacitor ripple increases significantly, potentially requiring either larger capacitors or alternative topologies.

Second, the arm inductor design requires careful optimization. While larger inductance values reduce circulating currents and limit fault current rise rates, they also increase the converter footprint, weight, and cost, and introduce a voltage drop that reduces the available AC voltage range. The typical inductance range of 0.1-0.18 p.u. represents a compromise between these competing requirements. For HVDC applications where transformer leakage inductance is already present, the total interface inductance (transformer plus arm inductor) must be considered in the control system design to avoid resonance with the submodule capacitor filters.

Third, the redundancy strategy directly affects both system availability and cost. MMC systems inherently support submodule redundancy by including one or more additional submodules per arm beyond the minimum number required for rated voltage operation. An N+1 or N+2 redundancy is typical for HVDC applications, enabling the converter to continue operating at full power after a single submodule failure without interruption. When a faulty submodule is detected (through voltage monitoring, temperature sensing, or communication loss), it is bypassed using a dedicated bypass switch or thyristor, and the remaining submodules adjust their voltage reference to compensate. The standard provides guidance on the relationship between redundancy level, submodule reliability (typically 500-1000 FIT per submodule), and the expected mean time between forced outages (MTBFO), enabling system planners to optimize capital expenditure against reliability targets.