Physical Address
304 North Cardinal St.
Dorchester Center, MA 02124
Physical Address
304 North Cardinal St.
Dorchester Center, MA 02124
IEC TR 62014-3:2002 introduces the Integrated Circuit Emission Model (ICEM), a behavioural modelling framework for simulating the electromagnetic interference (EMI) characteristics of integrated circuits. As ICs integrate more gates on faster silicon, predicting electromagnetic behaviour becomes essential for avoiding costly EMC failures during product development. This technical report, developed by IEC technical committee 93 on design automation, provides the foundational model for evaluating conducted and radiated emissions from IC internal activities and represents the state of the art in IC-level EMC modelling at the time of publication.
ICEM identifies three distinct mechanisms through which internal IC activities generate electromagnetic emissions, all addressed within a unified framework. The origin of parasitic emission lies in the current flowing through all IC gates during logic transitions. When hundreds of thousands of gates switch simultaneously at the clock edge, massive current spikes are created inside the die, inducing voltage drops in the internal voltage references. A modern IC integrating one million transistors can generate current peaks exceeding several amperes during clock edge transitions, with rise times as fast as 100 ps, creating broadband noise from DC to several gigahertz.
| Coupling Mechanism | Model Component | Emission Path | Frequency Range |
|---|---|---|---|
| Conducted via supply lines | Power-supply line model | Vdd/Vss pins to PCB power distribution network | DC – 1 GHz+ |
| Conducted via I/O lines | Input/output model | I/O pins to PCB traces and cables | DC – 1 GHz+ |
| Direct radiated emissions | Direct radiation model | IC package and die to free space | 30 MHz – 1 GHz+ |
The core of the ICEM model is the power-supply line model, consisting of a current generator (Ib) representing internal switching activity combined with RLC elements modelling the package, bonding wires, and on-chip interconnect. Primary resonance occurs between package inductance (LpackVdd, LpackVss) and parasitic capacitance (Cd) between Vdd and Vss pins, typically in the 10-100 MHz range. Secondary resonance involves on-chip series inductances (Lvdd, Lvss) and internal die capacitance (Cb), typically in the 100-1000 MHz range. A second-order model including both resonances provides significantly better correlation with measurements, particularly in the 100-1000 MHz range where secondary resonance can produce emission peaks 10-20 dB higher than first-order predictions.
| Parameter | Symbol | Description | Typical Range |
|---|---|---|---|
| Package inductance | LpackVdd/Vss | Lead frame or substrate inductance | 1 nH – 10 nH |
| Parasitic capacitance | Cd | Package pin-to-pin capacitance | 10 pF – 100 nF |
| Supply series resistance | Rvdd/vss | Bonding wire and die interconnect resistance | 0.1 Ohm – 10 Ohm |
| Supply series inductance | Lvdd/vss | Bonding wire and on-chip inductance | 1 nH – 20 nH |
| Internal die capacitance | Cb | On-chip decoupling capacitance | 10 pF – 100 nF |
The I/O coupling model addresses disturbances caused by internal voltage drops propagating through direct connections, parasitic coupling, and common impedance paths. PCB traces connected to I/Os act as antennas. The model supports both single-supply and multiple-supply structures, with substrate coupling impedance (Zsub) and I/O decoupling capacitance (Cio) as additional parameters. The direct radiation model is based on equivalent dipole representation, with parameters including internal currents, die size, internal loop areas, and package characteristics.
Parameter extraction can be performed through time-domain reflectometry (TDR) or network analyser measurements, or predicted from IC design tools that compute RLC parameters from geometrical and electrical characteristics. The current source Ib is described in piece-wise linear (PWL) format with amplitudes from several mA to 1 A, durations of 0.1 to 5 ns, and periods of 500 ps to 50 ns. These values depend closely on the software being executed on the IC. The standard provides typical value ranges and measurement methods for all model parameters.