IEC TR 61624: Nuclear Instrumentation — CAMAC Crate Controller and Dataway Protocol Guide

IEC TR 61624 is a technical report that provides detailed specifications for CAMAC crate controllers and the dataway protocol used in nuclear instrumentation systems. While IEC 60552 and IEEE 583 define the basic CAMAC standard, IEC TR 61624 extends these specifications with detailed implementation guidance for crate controller design, dataway timing optimization, interrupt handling, and system integration. This technical report is essential for engineers designing, maintaining, or extending CAMAC-based data acquisition systems in nuclear research facilities, fusion experiments, and accelerator installations.

Tip: IEC TR 61624 is closely related to IEC TR 61609 but focuses specifically on the crate controller implementation and dataway protocol details rather than the overall system architecture. The two documents are complementary — engineers should refer to both when developing CAMAC-based systems.

1. Crate Controller Functional Specifications

IEC TR 61624 defines three operational modes for CAMAC crate controllers: Type A (Simple), Type L (List), and Type U (Universal). Each type offers different levels of autonomy and intelligence, allowing system designers to select the appropriate controller for their application requirements.

Type A (Simple) Controller: The Type A controller is the most basic implementation, providing direct control of the dataway cycle under host computer command. It accepts command words from the host via the branch highway or a direct parallel interface and generates the corresponding dataway cycles (N, A, F selection, S1/S2 strobes, and data transfer). The Type A controller is suitable for systems where the host computer directly manages all data acquisition operations and the data rate requirements are moderate (typically less than 100,000 cycles per second).

Type L (List) Controller: The Type L controller includes an internal list processor that can autonomously execute a stored sequence of CAMAC operations. The list is loaded into the controller’s memory by the host computer, and once started, the controller executes the operations at maximum dataway speed without further host intervention. This dramatically reduces the host computer overhead and is essential for high-speed data acquisition applications. List lengths of up to 4,096 CAMAC commands are supported, with the list including jump, conditional branch, and loop instructions for flexible sequencing.

Type U (Universal) Controller: The Type U controller extends the Type L architecture with additional features including multiple list execution threads, real-time clock synchronization, event-driven operation, and direct memory access (DMA) to the host computer. The Type U controller is designed for the most demanding applications such as real-time plasma diagnostics in fusion experiments, where synchronized multi-chassis acquisition at rates exceeding 10⁶ dataway cycles per second is required.

Feature Type A (Simple) Type L (List) Type U (Universal)
Dataway cycle rate Up to 300 kHz Up to 1 MHz > 1 MHz
Autonomous operation None Stored list (up to 4K commands) Multi-thread, event-driven
DMA support No Optional Yes
LAM handling Polled Interrupt-driven with prioritization Vectored interrupt with nesting
Multi-crate support Via branch highway Via branch highway Multi-branch, multi-crate
Typical applications Slow monitoring, configuration Data acquisition, block transfer Real-time control, plasma diagnostics
Warning: The Type A controller, while simple and reliable, can become a bottleneck in systems with multiple fast ADCs. Each CAMAC cycle requires host computer intervention, and the branch highway handshake limits throughput to approximately 300 kHz even under optimal conditions. For systems with more than 4 fast digitizing modules, a Type L or Type U controller is strongly recommended.

2. Dataway Protocol Details

IEC TR 61624 provides detailed specifications for dataway timing that go beyond the basic standard. The dataway protocol is based on a handshake between the crate controller and the addressed module, with timing constraints that ensure reliable operation across the full range of module speeds and backplane configurations.

Standard Cycle Timing: The standard CAMAC dataway cycle consists of the following phases. Phase 1 (Selection): The controller asserts N, A, and F lines. Phase 2 (Module Response): Within 100 ns, the module asserts data on R lines (for read operations) or accepts data from W lines (for write operations), and asserts the Q and X response lines. Phase 3 (Strobe S1): After a settling time of at least 200 ns from the start of Phase 1, the controller asserts S1, which latches data in the module (for write operations) or in the controller (for read operations). Phase 4 (Strobe S2): After a delay of 200–400 ns from S1, the controller asserts S2, which clears temporary registers in the module. Phase 5 (Reset): The controller removes all signals, and after a 100 ns minimum dead time, the cycle can repeat.

Block Transfer (Q-Scan) Mode: The Q-scan mode enables efficient sequential data acquisition without software intervention. After each CAMAC cycle, the controller checks the Q response line. If Q = 1, the controller increments the subaddress (A) or station number (N) and initiates the next cycle. If Q = 0, the scan terminates. In Q-scan mode, the cycle repetition rate can reach 1 MHz because the controller does not need to fetch new command words from the host.

LAM Grading and Interrupt Handling: The report specifies a LAM grading scheme that assigns priority levels to each of the 16 possible LAM sources in a module. LAM source 1 has the highest priority (grade 1) and LAM source 16 has the lowest priority (grade 16). The crate controller collects all active LAM requests and presents the highest-priority graded LAM to the host computer via the branch highway. Nested interrupt handling — where a higher-priority LAM can interrupt the service routine of a lower-priority LAM — is supported in Type U controllers.

Design Insight: The timing of S1 and S2 strobes determines the CAMAC system’s speed limit. Under the standard specification, the minimum cycle time is approximately 1 μs (1 MHz maximum rate). However, by carefully designing the backplane (controlled impedance, proper termination, star grounding) and using modules with fast settling times, engineers have achieved cycle rates of 3–4 MHz in short crates with a limited number of modules. This is a legitimate optimization for applications requiring the maximum possible throughput from legacy CAMAC hardware.

3. Branch Highway and System Integration

IEC TR 61624 provides comprehensive specifications for the CAMAC Branch Highway that interconnects up to seven crates with a host computer. The highway uses a 66-conductor parallel cable with differential signal transmission for critical timing signals and single-ended TTL for data and address lines.

Cable Length and Termination: The maximum recommended cable length is 50 meters for the parallel branch highway. The cable must be terminated at both ends with the characteristic impedance of the cable (typically 100–120 Ω for the differential pairs and 50–75 Ω for the single-ended lines). The Branch Terminator is a passive device installed on the last crate in the highway chain that provides correct termination for all signal lines. Without proper termination, signal reflections cause data errors, spurious LAM interrupts, and unreliable crate selection.

Multi-Branch Systems: For systems requiring more than 7 crates, the report describes the use of multiple branch highways with a Branch Driver module in the host computer that manages up to 8 independent branches. Each branch supports up to 7 crates, for a total of up to 56 crates and approximately 1,288 module stations in a fully configured system.

Serial Highway Alternative: For installations requiring longer distances between crates and the host computer (up to 5 km), the report discusses serial CAMAC highways using coaxial cable or fiber optic links. The serial highway uses a byte-serial protocol that encapsulates dataway operations into serial frames. While the throughput is lower (typically 100–500 kB/s depending on cable length and bit rate), the serial highway enables distributed data acquisition across large facilities such as particle accelerators.

Tip: When installing a new CAMAC branch highway, use a time-domain reflectometer (TDR) to verify cable impedance and detect any impedance discontinuities at connectors. A common installation error is mixing cables with different characteristic impedances on the same branch, which creates reflection points that degrade signal quality. All cables on a branch should be from the same manufacturer and part number.

FAQs

Q1: Can a CAMAC Type A controller be upgraded to Type L functionality?
A: In most cases, no — the Type L controller requires on-board memory (RAM or ROM) for the list storage and an additional list processor (typically a dedicated microcontroller or sequencer). These hardware components are not present in Type A controllers. However, some manufacturers offered upgrade kits that replaced the Type A controller module with a Type L module in the same crate slot, preserving the existing backplane and modules.
Q2: What is the maximum number of modules that can be installed in a single CAMAC crate?
A: A standard CAMAC crate has 25 stations. Station 25 is always occupied by the crate controller, leaving 24 stations for user modules. However, practical limitations including power supply capacity (the crate backplane typically supplies +6V, -6V, +24V, and -24V at limited current), cooling capacity, and dataway loading (each module presents a capacitive load on the dataway lines) often limit populated crates to 15–20 modules. High-speed modules with significant power consumption may further reduce this number.
Q3: How does the CAMAC dataway ensure data integrity?
A: The X (Command Accepted) response line is the primary data integrity mechanism. After each CAMAC cycle, the controller checks that X = 1, confirming that the addressed module decoded the command correctly and executed it. If X = 0 (not accepted), the controller can retry the cycle or report an error. Additionally, the Q response provides status information that can verify data validity (e.g., Q = 1 = data ready, Q = 0 = no data). For critical applications, redundant read operations with comparison can be implemented at the system level.
Q4: What are the typical failure modes in aging CAMAC systems?
A: The most common failure modes include: (1) edge connector corrosion on module PCBs leading to intermittent contact; (2) deterioration of electrolytic capacitors in power supplies causing ripple and noise; (3) degradation of open-collector TTL drivers on dataway lines; (4) mechanical failure of crate backplane connectors (female DIN 41612 contacts losing spring tension); and (5) failure of the branch highway cable due to repeated flexing at connector junctions. Regular inspection schedules and spare module pools are essential for maintaining aging CAMAC installations.

© 2026 TNLab — Technical Knowledge Lab

Leave a Reply

Your email address will not be published. Required fields are marked *