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IEC 62373 – Bias-Temperature Stability Test for MOSFETs
IEC 62373 defines the standardised bias-temperature (BT) stability test method for MOSFET devices, which is one of the most critical reliability tests in semiconductor manufacturing. The BT test evaluates the stability of the threshold voltage (Vth) under simultaneous application of elevated temperature and gate bias, a stress condition that accelerates ion migration within the gate oxide layer. This standard is essential for process qualification, reliability monitoring, and technology benchmarking in the semiconductor industry.
💡 Key Insight: The bias-temperature instability (BTI) effect, particularly in its negative form (NBTI) for p-channel MOSFETs, has become the dominant reliability limitation in advanced CMOS technologies below 45 nm. IEC 62373 provides the foundational test methodology for quantifying this degradation mechanism.
1. Scope and Test Principle
The standard applies to all types of MOSFET devices, including both n-channel and p-channel types, discrete devices, and integrated circuit components. The BT stability test is performed by applying a constant gate voltage (typically the rated operating voltage or a multiple thereof) while the device is maintained at an elevated temperature (typically 125 °C to 250 °C depending on the technology) for a specified duration. The key measurement parameter is the shift in threshold voltage before and after the stress period.
The test principle is based on the following physical mechanisms:
- Ion migration: Mobile ions (primarily Na⁺, K⁺) within the gate oxide drift under the applied electric field toward the Si-SiO₂ interface, causing a shift in Vth
- Interface trap generation: Hot carriers and electrochemical reactions at the interface create new trapping states that alter the device characteristics
- Oxide trap charging: Charge trapping in pre-existing and stress-generated oxide defects contributes to the overall Vth shift
2. Test Equipment and Sample Preparation
The standard specifies detailed requirements for test equipment and sample handling to ensure reproducible results.
2.1 Equipment Requirements
| Parameter | Requirement | Recommended Specification |
|---|---|---|
| Temperature range | 25 °C to 300 °C | ±1 °C accuracy, ±0.5 °C stability |
| Gate voltage source | 0 to 100 V | ±0.1% accuracy, 0.1 mV resolution |
| Current measurement | 1 pA to 100 mA | ±0.5% accuracy, 0.1 pA resolution |
| Temperature ramp rate | < 10 °C/min | To avoid thermal shock |
| ESD protection | All terminals | < 100 V human body model |
2.2 Sample Handling
The standard emphasises the critical importance of electrostatic discharge (ESD) protection during sample handling and mounting. MOSFET gates have extremely thin oxide layers (typically 1.5-5 nm for advanced technologies) that can be permanently damaged by ESD events as low as 10 V. The standard requires ESD-protected workstations, grounded wrist straps, and conductive sample handling tools.
⚠️ Engineering Note: Package-related stress effects can confound BT test results. Plastic-encapsulated devices may exhibit additional Vth shifts due to moisture absorption and package-induced mechanical stress. For accurate intrinsic oxide reliability assessment, wafer-level testing or hermetic package testing is recommended.
3. Test Procedure and Data Analysis
The standard test procedure follows these steps:
- Initial measurement: Measure Vth at room temperature using a defined drain current criterion (typically 1 μA per μm of channel width)
- Stress application: Apply gate bias at elevated temperature for the specified duration (typically 168, 500, or 1000 hours)
- Read-point measurement: Measure Vth at the stress temperature within 30 seconds of removing bias (to minimise recovery effects)
- Final measurement: Measure Vth at room temperature after cooling and a 24-hour recovery period
- Data analysis: Calculate ΔVth and determine the degradation kinetics using power-law or logarithmic models
3.1 Test Circuit Configuration
The standard specifies separate configurations for n-channel and p-channel MOSFETs. For NBTI testing (p-channel), the gate is biased to the negative rail while source, drain, and substrate are grounded. For PBTI testing (n-channel), the gate is biased positively. The standard also addresses the special case of power MOSFETs where the body diode must be reverse-biased during stress.
🔥 Critical Consideration: The recovery effect (annealing) of BTI degradation upon removal of bias stress is a well-documented phenomenon that can cause up to 50% underestimation of degradation if read-point measurements are delayed. The 30-second maximum delay specified in the standard is a compromise between practical measurement constraints and accuracy requirements. For research-grade characterisation, on-the-fly (OTF) measurement techniques are recommended.
4. Wafer-Level Reliability Testing
Annex A of the standard provides guidance for wafer-level reliability (WLR) testing, which has become increasingly important for in-line process monitoring. WLR BT testing uses shorter stress times (typically 1-100 seconds at higher stress voltages) to achieve rapid feedback for manufacturing process control. The acceleration factors must be carefully validated against package-level results to ensure correlation.
✅ Best Practice: For comprehensive MOSFET reliability qualification, combine the IEC 62373 BT stability test with hot carrier injection (HCI) testing per JESD28 and time-dependent dielectric breakdown (TDDB) testing per IEC 62374. These three tests together cover the major gate oxide degradation mechanisms: ion migration, interface trap generation, and oxide breakdown.
5. Frequently Asked Questions
Q1: What is the acceptable threshold voltage shift limit for a qualified technology?
A: The acceptable ΔVth depends on the application. For digital logic, a 30 mV shift over 10 years is typically acceptable. For analogue/mixed-signal applications, the limit may be as low as 5 mV. The standard does not prescribe pass/fail criteria — these are determined by the manufacturer based on the target application.
A: The acceptable ΔVth depends on the application. For digital logic, a 30 mV shift over 10 years is typically acceptable. For analogue/mixed-signal applications, the limit may be as low as 5 mV. The standard does not prescribe pass/fail criteria — these are determined by the manufacturer based on the target application.
Q2: How does temperature acceleration work in BT testing?
A: The degradation follows an Arrhenius-type temperature dependence with activation energies typically in the range of 0.6-1.2 eV for NBTI and 0.8-1.5 eV for PBTI. At 150 °C, degradation proceeds approximately 100x faster than at 25 °C, enabling accelerated lifetime prediction.
A: The degradation follows an Arrhenius-type temperature dependence with activation energies typically in the range of 0.6-1.2 eV for NBTI and 0.8-1.5 eV for PBTI. At 150 °C, degradation proceeds approximately 100x faster than at 25 °C, enabling accelerated lifetime prediction.
Q3: What is the difference between NBTI and PBTI?
A: NBTI (negative bias temperature instability) affects p-channel MOSFETs with negative gate bias and is the dominant degradation mechanism in CMOS technologies. PBTI (positive bias temperature instability) affects n-channel MOSFETs with positive gate bias and has become more significant with the introduction of high-k dielectrics.
A: NBTI (negative bias temperature instability) affects p-channel MOSFETs with negative gate bias and is the dominant degradation mechanism in CMOS technologies. PBTI (positive bias temperature instability) affects n-channel MOSFETs with positive gate bias and has become more significant with the introduction of high-k dielectrics.
Q4: Why does the recovery effect matter for reliability assessment?
A: BTI degradation partially recovers when the bias stress is removed because trapped charges can detrap and interface states can anneal. If recovery is not accounted for, lifetime predictions may be overly optimistic. The IEC 62373 standard addresses this by specifying maximum measurement delay times.
A: BTI degradation partially recovers when the bias stress is removed because trapped charges can detrap and interface states can anneal. If recovery is not accounted for, lifetime predictions may be overly optimistic. The IEC 62373 standard addresses this by specifying maximum measurement delay times.
