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IEC 61958: Nuclear Instrumentation — CAMAC Multiple Controllers in a Single Crate
✅ Standard at a Glance
IEC 61958 (2000) specifies the requirements and operating modes for systems where multiple crate controllers operate within a single CAMAC crate. The standard CAMAC architecture defined in IEC 60516 (IEEE 583) assumes a single crate controller as the sole master of the crate dataway. However, as data acquisition systems grew more sophisticated in the 1980s and 1990s, applications emerged where multiple processors needed simultaneous access to modules in the same crate — for example, a primary controller handling online data collection while a secondary controller performs diagnostic readouts or calibration sequences without interrupting the primary data stream. IEC 61958 defines the priority arbitration mechanisms, bus access protocols, and timing requirements that enable up to eight controllers to share a single CAMAC crate bus reliably. The standard is closely related to IEEE 675 (Multiple controllers in a CAMAC crate).
IEC 61958 (2000) specifies the requirements and operating modes for systems where multiple crate controllers operate within a single CAMAC crate. The standard CAMAC architecture defined in IEC 60516 (IEEE 583) assumes a single crate controller as the sole master of the crate dataway. However, as data acquisition systems grew more sophisticated in the 1980s and 1990s, applications emerged where multiple processors needed simultaneous access to modules in the same crate — for example, a primary controller handling online data collection while a secondary controller performs diagnostic readouts or calibration sequences without interrupting the primary data stream. IEC 61958 defines the priority arbitration mechanisms, bus access protocols, and timing requirements that enable up to eight controllers to share a single CAMAC crate bus reliably. The standard is closely related to IEEE 675 (Multiple controllers in a CAMAC crate).
🔌 1. The Multiple-Controller Architecture
1.1 Motivation for Multiple Controllers
The single-crate-controller model of basic CAMAC works well for straightforward data acquisition but presents limitations in several important scenarios. In dual-port memory applications, one controller writes data into a memory module while a second controller reads data out for transmission, avoiding the data-buffering bottleneck of a single controller. In online/offline processing, one controller handles real-time data collection at the full trigger rate while a second controller performs slower analysis, histogramming, or data compression without stealing cycles from the real-time path. In diagnostic and calibration systems, a service controller can access any module in the crate for testing and calibration while the main data acquisition controller continues normal operation. In multi-experiment configurations, two independent experiments can share a single crate of modules, with each experiment controlled by its own crate controller that accesses only its assigned subset of modules.
IEC 61958 formalizes these use cases by defining a standard protocol for contention resolution and controller handover on the CAMAC dataway. Without this standardization, multiple-controller implementations were proprietary and incompatible between manufacturers. The standard enabled the development of multi-processor CAMAC systems that could be assembled from components of different vendors, dramatically expanding the application range of CAMAC.
| Parameter | Single-Controller (IEC 60516) | Multiple-Controller (IEC 61958) |
|---|---|---|
| Maximum number of controllers | 1 | 8 |
| Controller priority assignment | N/A (only one controller) | Hardware-determined priority (1 = highest, 8 = lowest) |
| Dataway mastership transfer time | N/A | <1 µs (between dataway cycles) |
| Addressing of controllers | Station 25 (fixed) | Station 25 + N-switch setting per controller |
| Inter-controller communication | N/A | Via crate Dataway or dedicated control lines |
| LAM (interrupt) handling | Single LAM grader | Shared LAM grader with controller-specific masks |
| Typical module access throughput | ~1 µs per CAMAC cycle | ~1 µs per CAMAC cycle (no overhead when uncontended) |
💡 Engineering Insight
The most technically challenging aspect of the multiple-controller CAMAC system is the dataway bus arbitration timing. The CAMAC dataway is a synchronous bus with S1 and S2 strobe pulses occurring at fixed intervals (typically 300 ns after command placement). When multiple controllers share the bus, the transition of mastership from one controller to another must occur during the inter-cycle gap — the period between the S2 strobe of one cycle and the command placement of the next cycle. IEC 61958 specifies that this transfer must complete in less than 400 ns. Achieving this with 1970s TTL logic was a significant engineering challenge, requiring dedicated priority-resolution hardware, open-collector bus drivers, and carefully designed bus termination. The standard’s timing specifications were derived from worst-case propagation delays across a fully loaded 25-station crate backplane.
The most technically challenging aspect of the multiple-controller CAMAC system is the dataway bus arbitration timing. The CAMAC dataway is a synchronous bus with S1 and S2 strobe pulses occurring at fixed intervals (typically 300 ns after command placement). When multiple controllers share the bus, the transition of mastership from one controller to another must occur during the inter-cycle gap — the period between the S2 strobe of one cycle and the command placement of the next cycle. IEC 61958 specifies that this transfer must complete in less than 400 ns. Achieving this with 1970s TTL logic was a significant engineering challenge, requiring dedicated priority-resolution hardware, open-collector bus drivers, and carefully designed bus termination. The standard’s timing specifications were derived from worst-case propagation delays across a fully loaded 25-station crate backplane.
1.2 Controller Types and Priority Scheme
IEC 61958 defines two fundamental types of crate controllers: Primary controllers (also called “A” controllers in some literature) which have the highest priority and are typically the main data acquisition controller, and Auxiliary controllers (type “B”) which have lower priority and serve specific functions such as diagnostic monitoring, calibration, or data compression. A primary controller can assert mastership of the dataway at any time when the bus is idle. An auxiliary controller must request mastership and wait for the primary controller to grant access. The priority is determined by position in the crate (station number) — the controller in the lowest-numbered station among those configured as controllers has the highest priority. This hardware-determined priority scheme ensures deterministic behavior without software configuration.
The standard also defines a priority interrupt (PI) mechanism that allows a high-priority controller to preempt a lower-priority controller in the middle of a block transfer by asserting the BUSY line on the dataway. The lower-priority controller must relinquish the bus within one CAMAC cycle of detecting the PI request. This enables time-critical operations — such as reading an ADC before its internal sample-and-hold capacitor begins to droop — to take priority over less time-sensitive operations.
⚠️ 2. Dataway Arbitration and Access Protocols
2.1 Bus Request and Grant Sequence
The dataway arbitration protocol defined in IEC 61958 uses a distributed daisy-chain approach. Each controller has a dedicated Bus Request (BRQ) output and a Bus Grant (BGT) input, connected in a daisy chain across the crate backplane from the highest-priority station to the lowest. When a controller needs to access the dataway, it asserts its BRQ line. The bus grant signal propagates from the highest-priority controller downward. Each controller blocks the grant if it has a pending bus request; otherwise, it passes the grant to the next controller in the chain. The controller that receives the grant while having a pending request becomes the bus master and may begin CAMAC cycles.
IEC 61958 specifies that the bus grant propagation delay through each controller must not exceed 25 ns, ensuring that the complete arbitration cycle (up to 8 controllers in the grant chain) completes within the inter-cycle gap of the dataway. The standard also defines a fairness mechanism — a controller that has just completed a dataway cycle must wait at least one idle period before reasserting its bus request, preventing a single high-priority controller from monopolizing the dataway indefinitely.
2.2 Inter-Controller Communication
In a multiple-controller crate, controllers often need to exchange status information, synchronization signals, and data. IEC 61958 defines several mechanisms for inter-controller communication. The shared memory approach uses a standard CAMAC memory module (typically a 24-bit wide RAM module) that can be accessed by any controller that gains bus mastership. The mailbox register approach uses specialized controller registers that appear as CAMAC stations and can be read or written by other controllers. The standard also defines the LL (Look-at-me Lock) mechanism for inter-controller interrupt signaling, where one controller can generate a LAM to another controller by writing to a specific control register.
⚠️ Design Warning
The most frequently encountered problem in multi-controller CAMAC installations is bus contention due to inadequate bus termination. When up to eight controllers share the dataway, the total capacitive load on the backplane can exceed 500 pF, causing signal reflections and timing violations if the bus is not properly terminated at both ends. IEC 61958 specifies that the dataway must be terminated with 100 Ω to +2 V at each end of the backplane. Field experience has shown that many commercial CAMAC crates, designed for single-controller operation, have only one terminator or none. Engineers configuring multi-controller systems must verify that both ends of the dataway have proper terminators installed. A second common issue is ground bounce in the backplane when multiple controllers drive the data lines simultaneously during the mastership handover period. Separate analog and digital ground planes within the crate backplane, connected at a single point, are recommended for reliable multi-controller operation.
The most frequently encountered problem in multi-controller CAMAC installations is bus contention due to inadequate bus termination. When up to eight controllers share the dataway, the total capacitive load on the backplane can exceed 500 pF, causing signal reflections and timing violations if the bus is not properly terminated at both ends. IEC 61958 specifies that the dataway must be terminated with 100 Ω to +2 V at each end of the backplane. Field experience has shown that many commercial CAMAC crates, designed for single-controller operation, have only one terminator or none. Engineers configuring multi-controller systems must verify that both ends of the dataway have proper terminators installed. A second common issue is ground bounce in the backplane when multiple controllers drive the data lines simultaneously during the mastership handover period. Separate analog and digital ground planes within the crate backplane, connected at a single point, are recommended for reliable multi-controller operation.
📈 3. Engineering Applications and System Integration
3.1 Dual-Port Memory and Pipelined Data Acquisition
One of the most powerful applications enabled by IEC 61958 is pipelined data acquisition using dual-port memory modules. In this configuration, Controller A (the primary, highest priority) reads data from ADC modules during the beam gate and writes it to a dual-port CAMAC memory module. Controller B (auxiliary) reads the data from the other port of the memory module during the inter-beam interval, processes it (formatting, compression, histogramming), and sends it to the host computer over a separate link (e.g., Ethernet or a dedicated serial highway). This pipeline architecture doubles the effective data throughput compared to a single-controller system where the controller must alternate between reading ADCs and transferring data to the host. The dual-port memory module is itself a CAMAC module that appears as two logical devices on the dataway, each with its own N, A address accessible by different controllers during different time slots.
3.2 Redundant and Fault-Tolerant Configurations
Another significant application is redundant data acquisition for safety-critical nuclear instrumentation. In a redundant configuration, two identical crate controllers operate in a “hot standby” mode. The primary controller handles all normal data acquisition. The standby controller monitors the primary controller’s activity via the inter-controller communication registers and the dataway activity lines. If the primary controller fails (detected by a watchdog timer or heartbeat signal), the standby controller assumes mastership of the dataway within a single inter-cycle gap (less than 1 microsecond), ensuring that no data is lost during the failover. This level of fault tolerance was critical for nuclear reactor safety monitoring systems and accelerator beam-loss monitoring systems, where an undetected controller failure could have serious consequences.
💡 Engineering Insight
For system integrators building multi-controller CAMAC systems, the key engineering decisions revolve around controller assignment and LAM distribution. Each CAMAC module in the crate generates LAM interrupts on the dataway LAM line (or, in later implementations, on a dedicated LAM line per station). In a single-controller system, all LAMs are routed to the one controller. In a multi-controller system, the LAM assignment must be carefully planned: which controller handles which module’s interrupts? IEC 61958 defines the LAM Gradder, a special CAMAC module (typically at station 26 or 27) that collects all 24 LAM lines from stations 1-24 and routes them to the appropriate controller based on mask registers. The gradder can be programmed to steer certain LAMs exclusively to certain controllers. A common mistake is configuring the LAM assignments without considering the servicing latency — a controller performing a long block transfer may not be able to service its assigned LAMs promptly, causing data overrun. Using a dedicated high-priority controller for time-critical LAM servicing, with separate controllers for data readout and data processing, is the recommended architecture for high-rate applications.
For system integrators building multi-controller CAMAC systems, the key engineering decisions revolve around controller assignment and LAM distribution. Each CAMAC module in the crate generates LAM interrupts on the dataway LAM line (or, in later implementations, on a dedicated LAM line per station). In a single-controller system, all LAMs are routed to the one controller. In a multi-controller system, the LAM assignment must be carefully planned: which controller handles which module’s interrupts? IEC 61958 defines the LAM Gradder, a special CAMAC module (typically at station 26 or 27) that collects all 24 LAM lines from stations 1-24 and routes them to the appropriate controller based on mask registers. The gradder can be programmed to steer certain LAMs exclusively to certain controllers. A common mistake is configuring the LAM assignments without considering the servicing latency — a controller performing a long block transfer may not be able to service its assigned LAMs promptly, causing data overrun. Using a dedicated high-priority controller for time-critical LAM servicing, with separate controllers for data readout and data processing, is the recommended architecture for high-rate applications.
❔ Frequently Asked Questions
1. How many controllers can operate in a single CAMAC crate per IEC 61958?
The standard supports up to eight controllers in a single CAMAC crate. The controllers occupy stations on the dataway (typically station 25 for the primary and adjacent stations for auxiliary controllers). Each controller must have a unique priority assignment determined by its physical position in the daisy-chain grant line, which runs across the backplane from the highest-priority to the lowest-priority station.
2. Can two controllers access the same CAMAC module simultaneously?
No, the CAMAC dataway is a single-master bus — only one controller can be master of the dataway at any instant and thus only one controller can access any module at a time. However, with the dual-port memory module defined in IEC 61958, two controllers can effectively access the same data set (though not the exact same memory location simultaneously) by using a memory module with two independent dataway ports. The arbitration between the two ports is handled within the dual-port memory module itself.
3. How does the priority arbitration work when multiple controllers request the bus simultaneously?
Priority arbitration uses a hardware daisy-chain mechanism. The bus grant signal propagates through each controller in sequence, starting from the highest-priority position. Each controller inhibits the grant propagation if it has a pending bus request, thereby claiming mastership. If two controllers request the bus at the same time, the one closer to the start of the grant chain (i.e., in the lower-numbered station) wins. The arbitration completes within 400 ns, fitting within the dataway inter-cycle gap and ensuring no loss of bus throughput.
4. What happened to CAMAC multiple-controller systems? Are they still in use?
Multiple-controller CAMAC systems were widely deployed in large physics laboratories (CERN, Fermilab, Brookhaven, KEK) and nuclear power plants from the mid-1980s through the 2000s. While most new installations have migrated to VMEbus, CompactPCI, or MTCA.4, many multi-controller CAMAC systems remain operational. The concepts standardized in IEC 61958 — specifically multi-master bus arbitration with daisy-chain priority, dual-port shared memory, and distributed interrupt handling — directly influenced the design of VMEbus multi-processor systems (IEC 60821) and are reflected in modern bus standards. The CAMAC implementation remains a reference example of a well-designed multi-master bus protocol for real-time data acquisition.
