IEC 61691-3-2:2001 — VHDL — Math Packages

Introduction

IEC 61691-3-2:2001, titled “Adoption of IEEE Std 1076.3-1997 — Standard VHDL Synthesis Packages,” specifies the standard mathematical packages for the VHDL hardware description language. This standard defines four key packages: std_logic_arith, std_logic_signed, std_logic_unsigned, and numeric_std, which provide signed and unsigned arithmetic operations, type conversion functions, and comparison operators for designs targeting logic synthesis.

Prior to this standard, VHDL designers were limited to bit and bit_vector types for numeric representation, which lacked the resolved-signal capabilities needed for realistic hardware modeling. The introduction of the std_logic family of types (IEEE 1164) created the need for arithmetic packages that could operate on these resolved types — a gap that IEC 61691-3-2 definitively filled. The standard has been instrumental in enabling VHDL-based digital signal processing, control system implementation, and algorithm acceleration on programmable logic.

Package Specifications

The std_logic_arith Package (Synopsys)

Originally developed by Synopsys and widely adopted before IEEE standardization, std_logic_arith defines distinct SIGNED and UNSIGNED types that are subtypes of std_logic_vector. It provides overloaded arithmetic, relational, and conversion operators. The package supports multiplication but with significant area implications — a 16×16 signed multiplier synthesized from this package typically consumes 200-400 logic cells in an FPGA.

The numeric_std Package (IEEE)

The IEEE-standard numeric_std package is the recommended replacement for the Synopsys packages in new designs. It defines the signed and unsigned types with a cleaner separation from std_logic_vector. Key advantages include: standardized overflow behavior, native shift operations, better synthesis tool compatibility, and a well-defined resize function that handles both truncation and saturation modes.

-- Example: Using numeric_std for a signed accumulator
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity accumulator is
  port (
    clk     : in  std_logic;
    rst     : in  std_logic;
    input   : in  signed(15 downto 0);
    output  : out signed(31 downto 0)
  );
end accumulator;

architecture behavioral of accumulator is
  signal sum : signed(31 downto 0) := (others => '0');
begin
  process(clk, rst)
  begin
    if rst = '1' then
      sum <= (others => '0');
    elsif rising_edge(clk) then
      -- Automatic sign extension for 16-bit to 32-bit
      sum <= sum + resize(input, 32);
    end if;
  end process;
  output <= sum;
end behavioral;

Fixed-Point and Floating-Point Extensions

Fixed-Point Arithmetic

While not part of the original IEC 61691-3-2:2001, the subsequent IEEE 1076.3 fixed-point packages (fixed_generic_pkg, fixed_float_types) build directly on the foundation established by this standard. The fixed-point approach represents numbers as sfixed or ufixed types with explicit integer and fractional bit widths. For example, sfixed(7 downto -8) represents an 8.8 signed fixed-point number with values from -128 to +127.9961 and a resolution of 2^-8 = 0.00390625.

Resource Utilization Comparison

Engineering Insights for VHDL Math Design

1. Bit Width Management and Overflow. The most common design error in VHDL arithmetic is improper bit width management. When adding two N-bit numbers, the result requires N+1 bits to avoid overflow. When multiplying N-bit and M-bit numbers, the result requires N+M bits. The numeric_std.resize function should be used explicitly for width adjustments, with careful selection between truncation and saturation overflow modes. Saturation arithmetic (where the result saturates at the maximum representable value) is preferred for control loops, while truncation (where overflow bits are discarded) is acceptable for signal processing where the least significant bits represent noise.

2. Synthesis Attributes for Arithmetic Optimization. Modern synthesis tools support attributes that control arithmetic implementation. The use_dsp48 attribute (Xilinx) or dsp_style attribute (Intel/Altera) directs the synthesis tool to map arithmetic operations to dedicated DSP blocks rather than distributed logic. Resource sharing attributes (resource_sharing) enable multiple arithmetic operations to share the same hardware, reducing area at the cost of throughput.

3. Pipelining for High-Speed Arithmetic. Arithmetic operations are often the critical path limiting maximum clock frequency. The standard approach is to insert pipeline registers at strategic points: between multiplication and addition in multiply-accumulate (MAC) operations, at the carry-chain boundaries in wide adders, and at the output of comparator trees. A 32-bit adder without pipelining may limit clock speed to 50-100 MHz in a typical FPGA; with 3-4 pipeline stages, the same adder can operate at 300-500 MHz.

4. Package Selection Strategy for Legacy Compatibility. When maintaining legacy VHDL code that uses std_logic_arith, it is often impractical to refactor to numeric_std. A practical strategy is to create a wrapper package that provides the Synopsys-style interface while internally using numeric_std functions. This enables gradual migration without breaking existing design blocks.

Frequently Asked Questions