IEC 61604: Nuclear Instrumentation — CAMAC Dataway and Crate System

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Historical Significance: CAMAC was the first standardized modular instrumentation system for data acquisition and control, developed jointly by the ESONE Committee (European) and the NIM Committee (US). First specified in 1969 (EUR 4100), CAMAC revolutionized nuclear physics experimentation by enabling interchangeable modules from different manufacturers to work together in a single crate. At CERN, CAMAC systems operated continuously for over 40 years in experiments like UA1 and UA2 that discovered the W and Z bosons.

Introduction to IEC 61604 (CAMAC)

IEC 61604, published in 1997 as the consolidated CAMAC standard, specifies the mechanical, electrical, and protocol specifications for the CAMAC (Computer Automated Measurement And Control) modular instrumentation system. Originally developed for nuclear physics data acquisition, CAMAC became the dominant modular instrumentation standard in laboratories worldwide from the 1970s through the 1990s, and remains in service in many legacy installations today.

The standard defines a complete system architecture consisting of a crate (a 19-inch rack-mountable chassis), a dataway (the backplane bus), a crate controller (the bus master), and up to 23 plug-in modules (the functional units). The system’s elegance lies in its simplicity: a well-defined parallel bus with 24 read lines (R), 24 write lines (W), 5 subaddress lines (A), 4 function lines (F), and robust handshaking control lines.

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Design Insight: The genius of CAMAC’s architecture was its creation of a clean separation between the dataway protocol (IEC 61604) and the module function (defined by application-specific supplemental standards). A single crate could simultaneously contain analog-to-digital converters, time-to-digital converters, scalers, discriminators, stepper motor controllers, and GPIB interfaces — all communicating over the same 86-wire dataway without protocol conflicts. This interoperability is something even modern standards struggle to achieve.

Dataway Architecture and Protocol

Bus Lines and Signals

The CAMAC dataway consists of 86 signal lines distributed across two 43-pin connectors on the backplane. These are organized into the following functional groups:

Signal Group	Lines	Direction	Description
Write lines (W1–W24)	24	Controller → Module	Data written from controller to module
Read lines (R1–R24)	24	Module → Controller	Data read from module to controller
Subaddress lines (A1–A5)	5	Controller → Module	Selects one of 32 internal registers within a module
Function lines (F1–F4)	4	Controller → Module	Selects one of 16 operations (read, write, clear, etc.)
Station number (N lines)	23	Controller → Module	Individual select line per slot (1 per station)
Command strobe (S1, S2)	2	Controller → Module	Timing strobes that execute the command
Busy (B)	1	Module → Controller	Crate busy indicator
Look-at-me (L)	23	Module → Controller	Interrupt request lines (1 per station)
Initialize (Z)	1	Controller → Module	System-wide reset
Clear (C)	1	Controller → Module	Clear selected modules
Inhibit (I)	1	Controller → Module	Disable module operations
Q response	1	Module → Controller	Module status response bit
X response	1	Module → Controller	Command accepted indicator

Dataway Cycle Timing

A CAMAC dataway operation follows a strict three-strobe timing sequence. The total cycle time for a basic operation is 1 μs (1 MHz data rate), although the standard allows for slower operation with modules that require longer access times. The sequence is:

Strobe 0: Address lines (N, A, F) are set up and allowed to settle for 200 ns min
Strobe 1 (S1): For write operations, data on W lines is latched into the module; for read operations, the module places data on R lines
Strobe 2 (S2): For read operations, the controller latches data from R lines; command termination is signaled

The Q and X responses must be valid by the end of S2. X=1 indicates the module recognized and accepted the command; X=0 indicates an invalid command or nonexistent module. Q provides application-specific status (e.g., data ready for a read operation).

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Engineering Insight — The X and Q Lines: The X response line is one of CAMAC’s most elegant features. It provides positive acknowledgment that the addressed module exists and that the specified function (F code) is valid for that module. This enables software to probe a crate and automatically discover which stations are populated and what commands they support — a precursor to the plug-and-play concept that would become ubiquitous decades later.

Crate Controller and System Architecture

Crate Controller Types

IEC 61604 defines two types of crate controllers for different system configurations:

Type	Description	Typical Application
Type A (Auxiliary Controller)	Parallel I/O to external computer via dedicated interface	Standalone system with dedicated computer
Type L (List-Sequencing Controller)	Branch highway via 66-conductor cable to remote computer	Multi-crate system with central computer
Type U (Universal Controller)	Multiple interface options including GPIB, VME, serial	Mixed-standard laboratory systems

Multi-Crate Systems

For large experiments, CAMAC supports multi-crate configurations using a branch highway (IEC 60552). A branch highway allows up to 7 crates to be connected to a single branch driver, with each crate identified by a 3-bit branch address. The branch highway uses a 66-conductor cable that extends the dataway signals, including a daisy-chained “Look-at-me” (LAM) priority arbitration system.

The standard also specifies the parallel branch driver and serial highway (IEC 60771) for geographically distributed systems. The serial highway uses byte-serial transmission over twisted-pair or coaxial cable at up to 5 MHz, supporting up to 62 crates over distances of several kilometers — an impressive capability for 1970s technology.

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Practical Note: CAMAC’s 1 μs cycle time was revolutionary in 1970 but imposes a maximum data throughput of approximately 1 MB/s per crate in continuous block-transfer mode. For modern applications requiring higher throughput, CAMAC modules were often used in conjunction with “list-sequencing” controllers that stored a sequence of CAMAC operations in local memory and executed them with DMA transfer to the host computer, achieving practical throughputs of 500 kB/s to 2 MB/s for repetitive readout sequences.

Mechanical Specifications and Power Distribution

IEC 61604 specifies precise mechanical dimensions and power distribution for the CAMAC crate:

Crate dimensions: Standard 19-inch rack width (482.6 mm), 6U height (266.7 mm), depth 350 mm minimum
Module width: Single-width module = 17.2 mm (0.6 inches); modules can be 1, 2, 3, 4, or 5 widths (multi-width modules use consecutive slots)
Backplane connectors: Two 43-pin connectors per station (86 pins total), with 0.1-inch pitch
Power supply: +6V at 25 A (typical), ±24V at 5 A (typical), +12V and -12V at 1 A (optional). The standard mandates sequencing: +6V must reach 95% of nominal before ±24V is applied
Cooling: Forced air cooling with airflow from bottom to top, minimum 200 CFM per crate

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Design Tip for Legacy Systems: When designing replacement modules for existing CAMAC crates, pay careful attention to the power supply sequencing requirement. Many CAMAC power supplies apply +6V and ±24V simultaneously, but module circuits often use the +6V rail for digital logic and the ±24V rails for analog circuitry. If the ±24V rails ramp up before the digital logic is stable, the analog outputs can produce unpredictable states that may damage downstream equipment. A simple power-on reset circuit with a 100 ms delay for the analog section is strongly recommended.

Addressing and Data Transfer Modes

Station Addressing

The crate has 25 station positions numbered 1–25. Station 24 and 25 are reserved for the crate controller and auxiliary controllers. Stations 1–23 are available for plug-in modules. Each station has an individual N (station select) line, so station selection is hardwired — no address decoding is required on the module.

Subaddress (A Lines)

Five subaddress lines (A1–A5, with A1 being the LSB) provide 32 internal register addresses per module. In practice, most modules use only a few subaddresses:

A(0): Typically the data register
A(1): Status/control register
A(2): Upper bits of a multi-word register
A(8)–A(15): Channel selection in a multi-channel module

Data Transfer Modes

IEC 61604 specifies three data transfer modes:

Mode	Description	Typical Rate
Single transfer (C × N · A · F)	One dataword per CAMAC command	~1 μs per word (1 MHz)
Block transfer (Q-stop)	Repeated execution of same command; module asserts Q=0 when done	~1 μs per word, up to 16k words
Stop-word transfer	Like Q-stop but uses a specific data pattern to terminate	~1 μs per word, variable length

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Timing Consideration: While the basic CAMAC cycle is 1 μs, practical system throughput is limited by cable delays in multi-crate systems and by software overhead in the controlling computer. A typical CAMAC system controlled by a PC via a GPIB-to-CAMAC interface achieves approximately 50–200 kB/s sustained throughput — far below the theoretical 1 MB/s. For high-speed data acquisition, a dedicated list-sequencing crate controller with DMA to the host computer is essential.

Legacy and Modern Relevance

While CAMAC has been largely superseded by VMEbus (IEC 60821), PCIe-based systems, and PXI (PCI eXtensions for Instrumentation), it maintains a significant presence in several domains:

Nuclear power plant safety monitoring: Many plants built in the 1980s–1990s still use CAMAC-based safety systems, with modernization plans extending to 2030+
Plasma fusion research: Tokamak facilities (JET, DIII-D, Tore Supra) have large installed bases of CAMAC modules for plasma diagnostics
Particle accelerator beam diagnostics: CERN, DESY, and other laboratories maintain CAMAC installations for legacy beam monitoring systems
Educational laboratory instruction: CAMAC’s transparent architecture makes it valuable for teaching nuclear instrumentation principles

The enduring value of IEC 61604 lies not in its technology (which is undeniably dated by modern standards) but in its design philosophy: a clean, well-defined hardware interface that enables modularity, interoperability, and long-term maintainability. These principles are as relevant today as they were in 1969, and they continue to influence modern standards like PXI, ATCA, and MicroTCA.

Frequently Asked Questions

Q: Can I mix CAMAC modules from different manufacturers in a single crate?

Yes — that was the entire point of the CAMAC standard. Any module that conforms to IEC 61604 will operate correctly in any CAMAC crate, regardless of manufacturer. The dataway protocol ensures interoperability through standardized timing, signal levels (TTL-compatible), and connector pin assignments. The only caveat is that multi-width modules must respect the slot numbering convention and must not bridge across the controller slots (24 and 25).

Q: What is the maximum number of CAMAC modules in a single system?

The serial highway standard (IEC 60771) allows up to 62 crates in a single system, each with up to 23 module slots (stations 1–23, with 24–25 reserved for controllers). This gives a theoretical maximum of 62 × 23 = 1,426 modules. In practice, the limiting factor is the LAM (Look-at-Me) interrupt arbitration time, which grows linearly with the number of crates on the serial highway. Systems with more than 20 crates are rare; most installations use 1–8 crates.

Q: What voltage levels does the CAMAC dataway use?

The CAMAC dataway uses standard TTL logic levels: logic 0 = 0 V to +0.8 V, logic 1 = +2.0 V to +5.25 V (with +5 V being nominal). The dataway’s W, R, N, A, and F lines use 3-state TTL drivers on the source side. The Q and X response lines use open-collector TTL. Signal termination is provided by resistor packs at the end of the backplane (typically 180 Ω to +5 V and 220 Ω to ground).

Q: Is there a modern FPGA-based CAMAC controller available for legacy system upgrades?

Yes. Several companies offer USB-CAMAC and Ethernet-CAMAC controllers based on FPGA implementations of the crate controller logic. These typically use a small FPGA (Xilinx Spartan-6 or similar) to implement the dataway timing generator, LAM handler, and a FIFO buffer, with a USB 3.0 or Gigabit Ethernet interface to the host computer. These modern controllers can increase data throughput from legacy 50 kB/s (GPIB-CAMAC) to over 2 MB/s while maintaining full compatibility with existing CAMAC modules. This is often the most cost-effective upgrade path for laboratories with large CAMAC investments.