IEC 61523-2: Delay and Power Calculation Standards for CMOS ASIC Libraries

Tip: IEC 61523-2 (also known as IEEE 1481) defines a standardized pre-layout delay calculation specification for CMOS ASIC libraries. It introduces the Delay Calculation Language (DCL) for modeling timing and power characteristics of digital cells, enabling interoperable EDA tool flows.

Scope and Industry Context

IEC 61523-2, published in 2002 as a dual-logo standard with IEEE (Std 1481-1999), specifies a comprehensive methodology for pre-layout delay and power calculation in CMOS ASIC design flows. The standard is part of the IEC 61523 series (Delay and Power Calculation Standards), which includes Part 1 (Delay Calculation DCL), Part 3 (IEEE 1497 — Standard Delay Format SDF), and Part 4 (DCL and Liberty integration). IEC 61523-2 focuses specifically on pre-layout delay modeling for CMOS ASIC libraries, providing a standardized representation of timing arcs, cell state dependencies, and interconnect effects before physical design.

The standard addresses a critical challenge in deep submicron (DSM) VLSI design: the increasing disparity between intrinsic gate delay and interconnect delay. As process geometries shrank below 0.5 μm, wire delays began to dominate path timing, requiring sophisticated delay models that account for input slew rate, output load capacitance, and multiple input switching (MIS) effects. IEC 61523-2 provides the mathematical framework and language syntax to capture these dependencies in a technology-independent manner.

Warning: IEC 61523-2 pre-layout models do not account for post-layout effects such as coupling capacitance, IR drop, and temperature inversion. Pre-layout timing estimates can differ from silicon-measured delays by 20-40% at 28 nm and below. Always perform post-layout STA signoff using extracted parasitics (SDF/SPEF) before tapeout.

Delay Calculation Language (DCL) Framework

The core innovation of IEC 61523-2 is the Delay Calculation Language (DCL), a declarative modeling language for representing timing and power characteristics of digital cells. DCL uses a table-based approach with interpolation functions to characterize cell delay, output slew, and power dissipation across operating conditions.

DCL Element Type	Symbol	Description	Example
Timing coefficient table	tpdCoeffTable	2D table of propagation delay vs. input slew and output load	4×5 matrix (4 input slews, 5 load values)
Interpolation function	interp	Bilinear or bicubic interpolation between tabulated values	selectPlane + planar interp
State-dependent group	when	Conditional delay selection based on cell state	when (A=1 & B=0) delay = value
Switching power	Psw	Dynamic power = 0.5 * C_load * Vdd^2 * f_sw	Per-input pin power model
Leakage power	Pleak	Static power = I_leak * Vdd, state-dependent	Table for each input state

The DCL tables are defined using a specific file format consisting of keyword-delimited blocks. Each timing arc (e.g., input pin A to output pin Y) has associated coefficient tables for four transition types: RP (rise propagation), RT (rise transition), FP (fall propagation), and FT (fall transition). These tables typically contain 20 entries arranged in a 5×4 or 4×5 matrix corresponding to different input slew rates and output load capacitances.

/* Example DCL fragment for an inverter */
calc(TimingModel): {
/* RP case — Rise Propagation delay */
inv.a.yn.RP.”1″.”1″: 0.1033;
inv.a.yn.RP.”1″.”2″: 0.1812;
…
inv.a.yn.RP.”5″.”4″: 3.8040;

/* Plane selection for interpolation */
calc(selectPlane):
passed(string: coeffType, integer: row, column);
…
when (Z10+Z01-Z00 < Z11) result(integer: 1); otherwise result(integer: -1); }

Engineering Insight: The interpolation scheme in DCL is critical for accurate delay calculation. IEC 61523-2 specifies a bilinear interpolation method that uses a four-point weighted average from the surrounding table entries. However, for high-speed cells where delay varies nonlinearly with load, a bicubic interpolation or a lookup table with finer granularity (e.g., 7×7 instead of 5×4) may be required to achieve ±5% accuracy. When developing library characterization data, always verify that the table granularity captures the nonlinear regions of the delay surface.

Interconnect Modeling and Pre-Layout Estimation

A key contribution of IEC 61523-2 is its treatment of interconnect delay estimation before physical layout is available. The standard defines a wire-load model (WLM) methodology that estimates interconnect capacitance and resistance based on fanout, block size, and process technology parameters. These models enable designers to make timing-aware decisions during logic synthesis and floorplanning, long before detailed routing.

Fanout Range	Estimated Wire Length (μm)	Estimated Capacitance (fF)	Estimated Resistance (Ω)	RC Delay Contribution (ps)
1	50 – 100	10 – 20	5 – 10	0.5 – 2
2	100 – 250	20 – 50	10 – 25	2 – 10
4	250 – 600	50 – 120	25 – 60	10 – 50
8	600 – 1500	120 – 300	60 – 150	50 – 200
16	1500 – 4000	300 – 800	150 – 400	200 – 1500

As process nodes advanced to 65 nm and below, the traditional WLM approach became increasingly inaccurate because wire delay is not simply a function of fanout — it depends on routing topology, layer assignment, via count, and coupling to adjacent nets. The industry has largely moved to physical synthesis (place-and-route based timing estimation) even at the pre-layout stage, though the fundamental DCL framework for cell-level timing characterization remains relevant and is incorporated into Liberty (.lib) models.

Danger: Relying solely on pre-layout WLM-based timing analysis for signoff at advanced nodes (28 nm and below) is a known cause of silicon failures. The error between pre-layout WLM estimates and post-layout extracted timing can exceed 50% for critical paths, particularly those with high fanout or long routes. Always require a post-layout timing signoff with SPEF-annotated SDF before tapeout. For safety-critical or high-reliability designs, add a 20-30% timing margin to pre-layout estimates to account for unmodeled coupling effects.

Q1: What is the relationship between IEC 61523-2 and IEEE 1481?

IEC 61523-2 and IEEE 1481 are essentially the same standard, published jointly to ensure global adoption. IEC 61523-2:2002 corresponds to IEEE Std 1481-1999 with identical technical content. The IEC version is more widely referenced in Europe and Asia, while the IEEE version is standard in North America. Both use the same DCL syntax and timing model specifications.

Q2: How does IEC 61523-2 handle multiple input switching (MIS) effects?

The standard provides mechanisms for modeling MIS effects where simultaneous switching of multiple inputs affects propagation delay. DCL supports conditional delay tables (using “when” clauses) that select different timing coefficients based on the state of other inputs. However, full MIS modeling requires characterization of each possible input combination, which grows exponentially with the number of inputs. In practice, most library characterizations only model single-input switching (SIS) and add a guard band for MIS effects.

Q3: Can IEC 61523-2 be used for non-CMOS technologies like FinFET?

Yes, the DCL framework is technology-agnostic and has been successfully applied to FinFET (16 nm, 7 nm, 5 nm) library characterization. However, FinFET devices introduce additional effects not explicitly addressed by the original standard, such as self-heating, bias temperature instability (BTI) aging, and increased leakage variability. Modern Liberty (.lib) models extend the DCL concept with additional constructs for these effects while maintaining backward compatibility with the IEC 61523-2 framework.

Q4: How does power calculation in IEC 61523-2 differ between static and dynamic power?

IEC 61523-2 models dynamic (switching) power as a function of output load capacitance, supply voltage, and switching frequency, consistent with the classic 0.5*C*V²*f formula. Leakage (static) power is modeled as state-dependent current draw, with separate values for each stable input combination. The standard also supports internal power modeling, where power consumed within the cell (short-circuit power) is characterized as a function of input slew and output load, independent of the load charging current.