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IEC 61189 โ Test Methods for Electrical Materials, Printed Boards and Interconnection Structures: A Complete Engineering Guide
If you design, manufacture, or qualify printed circuit boards and electronic assemblies, IEC 61189 is the definitive international standard framework for verifying that your materials, processes, and final products meet global reliability requirements. This series is the IEC counterpart to IPC-TM-650 and is widely referenced in automotive (IATF 16949), aerospace, medical, and industrial electronics sectors.
1. Overview and Structure of the IEC 61189 Series
IEC 61189 is a multi-part international standard that specifies a comprehensive suite of test methods for evaluating the performance, quality, and long-term reliability of electrical materials, printed boards (PCBs), interconnection structures, and electronic assemblies. Unlike a product specification that sets pass/fail criteria, IEC 61189 focuses exclusively on how to conduct tests — making it an indispensable reference for quality assurance laboratories, failure analysis teams, and process engineering groups worldwide.
The standard is organized into six distinct parts, each addressing a specific category of materials or structures:
| Part | Title | Key Focus Areas |
|---|---|---|
| IEC 61189-1 | General | Definitions, test hierarchies, environmental classifications, sampling plans, and general requirements common to all test methods |
| IEC 61189-2 | Test methods for materials | Copper foil properties, prepreg resin flow/ gel time, laminate dielectric constant and dissipation factor, surface resistivity, volume resistivity, CTI (Comparative Tracking Index), and thermal analysis (Tg, Td, TMA) |
| IEC 61189-3 | Test methods for printed boards | Solderability, microsectioning, dimensional stability, plating adhesion, impedance measurement, bow and twist, cleanliness testing, and solder mask adhesion |
| IEC 61189-5 | Test methods for soldering materials and fluxes | Solder paste spread and slump, flux activity and halide content, spattering, tackiness, and solder ball testing |
| IEC 61189-6 | Test methods for embedded passive components | Embedded resistor and capacitor testing, buried component reliability, and substrate compatibility |
Note that IEC 61189-4 (originally intended for interconnection structure assemblies) had its content either merged into Part 3 or left for future revision. Always verify the latest edition on the IEC webstore before specifying test methods for a qualification plan.
The relationship between IEC 61189 and the IPC-TM-650 test methods family is complementary rather than competitive. Many test procedures are harmonized at the technical level, but key differences exist in measurement locations, specimen conditioning, and acceptance criteria — a point we explore in detail below.
2. Core Test Methods in Depth
2.1 Solderability Testing
Solderability testing determines how well PCB lands, plated-through holes (PTHs), and component terminations are wetted by molten solder — a fundamental prerequisite for forming reliable solder joints. IEC 61189-3 specifies two primary methods:
- Dip and Look (Qualitative): The test coupon is dipped in flux, immersed in molten solder at a specified temperature (235 °C for SnPb eutectic, 245–260 °C for lead-free SAC alloys) for 5±0.5 seconds, then visually inspected. Complete, smooth wetting across at least 95% of the test area constitutes a pass. Non-wetting or dewetting indicates oxidation, contamination, or improper surface finish.
- Wetting Balance (Quantitative): A force transducer measures the wetting force as a specimen is immersed in solder at a controlled rate. Key metrics include wetting time (t₀), maximum wetting force (Fmax), and wetting angle. This method is especially valuable for evaluating different surface finishes (ENIG, HASL, OSP, immersion tin) under controlled aging conditions.
In practice, the wetting balance method provides far more actionable process control data than the dip-and-look approach. A shift in t₀ from 1.2 s to 2.8 s over a production run is an early warning signal for surface finish degradation or flux activity loss — long before visual defects appear. We recommend implementing wetting balance testing as a periodic process monitor for high-reliability assembly lines.
A critical nuance often overlooked by engineers is the aging preconditioning requirement. Both IEC 61189-3 and IPC J-STD-003 specify steam aging (4 or 8 hours at 93 °C / 85% RH) to simulate the natural oxidation that occurs between PCB fabrication and assembly. Boards tested without proper aging may pass solderability testing yet fail catastrophically on the production line after weeks of storage.
2.2 Surface Insulation Resistance (SIR)
SIR testing assesses the cleanliness and long-term reliability of PCB assemblies by measuring the resistance between adjacent conductors under biased temperature-humidity conditions. It is the single most effective test for detecting ionic contamination, poorly cured solder mask, and electrochemical migration (dendrite growth) risk.
The standard test procedure per IEC 61189-3 uses interdigitated comb patterns (typically IPC B-25 or IPC-B-24 test vehicles):
- Bias voltage: 50 V or 100 V DC
- Environmental chamber: 85 °C / 85% RH
- Test duration: 168 hours (7 days) for standard qualification; 500–1000 hours for high-reliability applications
- Measurement intervals: resistance recorded at 0, 24, 96, and 168 hours
| Condition | Acceptable SIR (Ω) | Industry Implication |
|---|---|---|
| Initial (0 h) | ≥ 1 × 10⁶ | Baseline cleanliness — no ionic residues |
| After 168 h at 85/85 | ≥ 1 × 10 | Adequate solder mask cure and cleaning process |
| Sustained drop > 2 decades | < 1 × 10⁶ | High risk of CAF or dendritic growth — investigate process |
| Recovery after drying | ≥ 1 × 10⁶ | Reversible moisture absorption (acceptable for most classes) |
A common pitfall: SIR testing on bare boards (without solder mask) often yields misleadingly high readings because there is no mask to trap ionic residues. Per IEC 61189-3, all SIR tests should be performed on fully processed boards with solder mask applied and cured. Testing bare laminate alone does not represent real-world assembly conditions and can mask serious process deficiencies.
2.3 Thermal Stress Testing and the Solder Float Method
Thermal stress testing simulates the extreme thermal shock that PCB materials endure during wave soldering, reflow, and rework operations. The most widely used method is the solder float test (IEC 61189-3-710, harmonized with IPC-TM-650 2.6.8):
- A test coupon (typically 25 mm × 25 mm containing multiple PTHs of varying diameters) is pre-dried at 105–150 °C for 4–6 hours to drive out absorbed moisture.
- The coupon is floated on molten solder at 288 °C ± 5 °C for 10 ± 1 seconds.
- After cooling to room temperature, the coupon is subjected to microsectioning to inspect for internal damage.
The failure modes detected by thermal stress testing include:
- Barrel cracking: Plated copper fractures in the PTH barrel, typically at the middle or at the knee (corner where barrel meets the land). Cracking at the knee is more critical as it directly compromises interconnect reliability.
- Innerlayer separation: The bond between the PTH plating and the inner copper layer fails, often caused by inadequate resin removal during desmear or insufficient copper nucleation in the electroless process.
- Blistering and measling: Localized delamination within the laminate substrate, visible as white spots or raised areas. Measling (discrete white spots along the glass weave) is generally cosmetic, but blistering (raised, delaminated areas) is a rejectable defect.
For high-layer-count boards (16+ layers) or boards with thick copper (>2 oz / 70 µm), consider using the thermal shock (TCT) method instead of the solder float. The solder float test applies a single, intense thermal pulse that may not accurately reflect the cumulative fatigue damage from multiple reflow cycles. TCT cycling between -55 °C and +125 °C for 100–500 cycles provides a more realistic assessment of barrel fatigue life.
2.4 Microsectioning — The Gold Standard for Physical Analysis
Microsectioning is the definitive analytical technique for evaluating the internal quality of a PCB. While it is a destructive test, the information it yields about plating quality, layer registration, and internal voiding is unmatched by any non-destructive method.
The procedure per IEC 61189-3-705 follows these steps:
- Specimen extraction: A coupon containing features of interest (vias, PTHs, surface lands) is cut from the panel using a precision saw or router.
- Mounting: The coupon is encapsulated in epoxy or acrylic resin under vacuum to ensure complete void-free impregnation of holes and cavities.
- Sectioning and polishing: The mounted specimen is cross-sectioned at the target plane (typically the centerline of a PTH row) and progressively polished through 600, 1200, and 2400 grit SiC paper, followed by 1 µm and 0.05 µm alumina or diamond suspensions.
- Microscopic examination: The polished cross-section is examined at 50×–500× magnification using calibrated measurement software.
| Measurement Parameter | IEC 61189 Requirement | IPC-A-600 Requirement | Engineering Note |
|---|---|---|---|
| Minimum PTH copper plating | ≥ 20 µm (center of barrel) | ≥ 20 µm (thinnest point) | IPC measures at the knee, which is usually the thinnest area. IEC measurement at the barrel center may overstate margin in boards with poor throwing power. |
| Dielectric thickness (prepreg) | ±15% of nominal | ±20% of nominal | IEC tolerance is tighter — important for controlled impedance designs. |
| Inner layer registration | ≤ 75 µm offset | ≤ 100 µm offset | IEC is again tighter, critical for HDI and microvia alignment. |
| Etchback (desmear removal) | 5–80 µm | 3–80 µm | Insufficient etchback is a leading cause of innerlayer voiding in high-aspect-ratio boards. |
One of the most valuable measurements often overlooked in routine microsectioning is the copper ductility and elongation of the PTH barrel plating. A microsection etched with a dilute ammonium persulfate solution reveals the grain structure of the electrodeposited copper. Fine equiaxed grains indicate good ductility (≥ 12% elongation), while columnar or layered structures may indicate brittle plating prone to cracking under thermal stress. We recommend including a grain structure evaluation in any first-article qualification microsectioning plan.
3. IEC 61189 vs IPC-TM-650: A Practical Comparison
Engineers working across global supply chains inevitably encounter both IEC 61189 and IPC-TM-650 test methods. While the two families share test philosophy and many procedural details, important differences exist:
| Aspect | IEC 61189 | IPC-TM-650 | Impact on Design/Qualification |
|---|---|---|---|
| Barrel copper measurement | Center of barrel | Thinnest point (knee) | Boards passing IEC alone may fail IPC; specify both for high-reliability applications. |
| Solder aging preconditioning | 4 h or 8 h steam age | 8 h steam age (Class 2/3) | IPC requires longer aging for Class 3; adjust test plans accordingly. |
| SIR test duration | 168 h minimum | 168 h (168 h optional extension for Class 3) | Largely harmonized; main difference is in pattern geometry. |
| Thermal stress temperature | 288 °C for 10 s | 288 °C for 10 s | Harmonized; but IPC adds preconditioning bake at 150 °C for 6 h. |
| Acceptance criteria | Referenced in product spec | Defined in IPC-6012 | IPC has explicit pass/fail tables; IEC defers to the referencing specification. |
A critical real-world scenario: A European medical device OEM specifies IEC 61189 for incoming PCB qualification, while their Asian contract manufacturer uses IPC-6012 Class 3 as their internal standard. The barrel copper measurement conflict (center vs. thinnest point) has caused repeated disputes over plating quality. The resolution is to explicitly state in the procurement specification: “PTH copper thickness shall meet both IEC 61189-3 barrel center ≥ 20 µm and IPC-6012 Class 3 thinnest point ≥ 18 µm.” This dual-spec approach eliminates ambiguity.
4. Engineering Design Insights
Beyond the test procedures themselves, IEC 61189 provides a framework for building reliability into the design and manufacturing process. Here are four actionable insights distilled from years of working with the standard:
1. Design the test coupon alongside the product. One of the most common mistakes is designing the PCB first and only then realizing that no suitable coupon area exists for the required test methods. IEC 61189-1 provides guidance on coupon placement and feature requirements. Incorporate dedicated test coupons into the panel layout from day one — ideally with IPC-B-25 comb patterns for SIR, microsection targets at multiple PTH diameters (0.3 mm, 0.6 mm, 1.0 mm), and solderability test lands with representative surface finishes.
2. Thermal stress and SIR are orthogonal reliability indicators. A board with excellent thermal stress performance (no cracking after 6× solder float) can still fail catastrophically in SIR testing if the solder mask is undercured or if ionic residues from insufficient cleaning remain. These two tests probe entirely different failure mechanisms (thermomechanical vs. electrochemical), and both must pass for a reliable product.
3. Microsectioning data drives process improvement. Tracking microsection measurements over time — not just pass/fail — reveals process drift long before it produces out-of-spec conditions. For example, a gradual decrease in average PTH copper thickness from 27 µm to 22 µm over three months may indicate aging bath chemistry in the electroplating line, declining anode area, or increasing bath contamination. Early intervention prevents scrap.
4. CAF testing as an extension of SIR. While IEC 61189 does not yet have a dedicated CAF (Conductive Anodic Filament) test method, the SIR framework can be extended to CAF evaluation by using daisy-chain coupons with closely spaced (0.3–0.5 mm) PTH strings biased at 100–500 V under 85/85 conditions for 500+ hours. Consider this for high-reliability products (automotive, aerospace, medical) operating in humid environments.
For engineering teams new to IEC 61189, we recommend starting with a “Tier 1” test suite comprising: solderability (dip and look), SIR (168 h at 85/85), thermal stress (solder float at 288 °C), and microsectioning (plating thickness and registration). This four-test combination covers the most common failure modes in PCB assembly and provides a solid foundation for quality assurance.
5. Frequently Asked Questions
Q1: Is IEC 61189 mandatory for CE marking of electronic products?
No, IEC 61189 is not directly listed as a harmonized standard under the EU Low Voltage Directive or EMC Directive. However, it is widely referenced in product-specific standards and is considered best practice for demonstrating due diligence in quality assurance. Many notified bodies and technical assessment organizations accept IEC 61189 test reports as supporting evidence for conformity assessments.
Q2: What is the difference between IEC 61189-2 and IEC 61189-3?
IEC 61189-2 covers test methods for the raw materials used to manufacture interconnection structures — copper foil, prepreg, laminate, solder mask, and conformal coatings. IEC 61189-3 covers test methods for the finished printed board itself, including dimensional, mechanical, electrical, and environmental tests. In short: Part 2 = material qualification, Part 3 = product verification.
Q3: Can IEC 61189 test methods be used for flexible circuits?
Yes, with modifications. Many test methods in IEC 61189-3 are applicable to flexible PCBs, but special attention must be paid to specimen preparation (flexible materials require rigidization before microsectioning) and thermal stress conditions (lower temperatures may be needed for adhesive-based flex materials). IEC 61189-3 includes annexes with guidance for flexible circuit testing.
Q4: How does IEC 61189 handle high-frequency (RF/microwave) material testing?
IEC 61189-2 includes test methods for dielectric constant (Dk) and dissipation factor (Df) using both stripline and split-post dielectric resonator techniques at frequencies up to 10 GHz and beyond. For millimeter-wave applications (5G, automotive radar), the standard recommends the split-cylinder resonator method (IEC 61189-2-721) which provides accurate Dk/Df measurements up to 100 GHz. These methods are harmonized with IPC-TM-650 2.5.5.5 and 2.5.5.13.
