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IEC 14776-112-04: SCSI Parallel Interface-2 (SPI-2) – Technical Overview and Compliance
Comprehensive Guide to the SCSI Parallel Interface Standard for High-Performance Storage Systems
The IEC 14776 series defines the Small Computer System Interface (SCSI) protocol and physical layer standards. Within this family, IEC 14776-112-04 (also adopted as CAN/CSA-ISO/IEC 14776-112-04 in Canada) addresses the SCSI Parallel Interface-2 (SPI-2). This standard specifies the electrical, timing, and protocol requirements for high-speed parallel interconnections between hosts and peripheral devices, supporting data rates up to 80 MB/s in wide configuration. This article provides a detailed technical examination of the scope, critical specifications, implementation highlights, and compliance notes for SPI-2.
Scope and Purpose
IEC 14776-112-04 defines a parallel bus architecture that allows multiple initiators and targets to communicate over a shared set of signal lines. The standard covers three signaling technologies:
- Single-Ended (SE) – Low-cost, limited distance (up to 3 m at Fast-40).
- High-Voltage Differential (HVD) – Legacy differential signaling with up to 25 m cable length.
- Low-Voltage Differential (LVD) – Modern low-power signalling supporting up to 12 m and speeds up to 80 MB/s.
The purpose of the standard is to ensure interoperable electrical behaviour, deterministic bus arbitration, and reliable data transfer across a range of system configurations. It supersedes earlier SPI (SCSI-3) specifications and tightens timing margins for higher-speed operation.
Technical Requirements and Specifications
Electrical Interface
The SPI-2 standard defines driver output characteristics, receiver thresholds, and termination requirements for each signalling mode. LVD is the predominant mode for modern designs because of its balance between speed and power.
| Parameter | Single-Ended (SE) | High-Voltage Differential (HVD) | Low-Voltage Differential (LVD) |
|---|---|---|---|
| Max data rate (wide) | 40 MB/s | 40 MB/s | 80 MB/s |
| Max cable length | 3 m | 25 m | 12 m |
| Common-mode voltage | 0 V | ±7 V | ±1.9 V |
| Differential voltage swing | N/A | ≥2 V | 0.5 V to 1.9 V |
| Termination | Active (1.27 V regulator) | Passive (330 Ω/220 Ω) | Active (1.25 V regulator) |
| Receiver threshold | 0.8 V / 2.0 V | ±0.3 V differential | ±0.1 V differential |
Important: Mixing SE, HVD, and LVD devices on the same bus segment is not permitted by the standard. An LVD bus can be made SE-compatible only through the use of a protocol-based negotiation mechanism (LVD/SE handshake).
Protocol and Timing
The standard retains the SCSI-3 architecture of bus phases: Bus Free, Arbitration (optional for single-initiator), Selection/Reselection, Command, Data, Status, and Message. Key timing parameters include:
- Data setup/hold times: For Fast-40 (80 MB/s), data valid to REQ/ACK assertion window is 10 ns minimum.
- REQ/ACK skew: Must be ≤ 5 ns to maintain synchronous offset alignment.
- Bus settle delay: After bus free, at least 400 ns before next assertion of any signal.
Cable and Connector Requirements
SPI-2 mandates use of 68-pin alternative connector (D-shell or high-density) for wide bus configurations. Cables must meet controlled impedance (95 Ω ± 10 Ω differential for LVD) and cross‑talk limits. Maximum stub length from the bus to any transceiver is limited to 0.1 m for Fast-40 operation.
Implementation Considerations and Design Highlights
Tip: For highest signal integrity, implement point-to-point termination using active terminator ICs that provide the precise 1.25 V reference required by LVD. Avoid daisy‑chaining more than 16 devices physically – use expanders only if the standard’s timing can be guaranteed.
System designers should pay close attention to:
- Stub length: Keep stubs as short as possible; use DIP‑style transceivers placed directly on the bus traces.
- Grounding: Use a solid, low-inductance ground plane. The standard requires the cable shield to be grounded at the host end only to avoid ground loops.
- Termination power: TERMPWR must be supplied by at least two devices on the bus; each provider must source no more than 1.5 A.
- EMI filtering: Common‑mode chokes on the bus lines are permissible only if they do not degrade the rise‑time (≤ 10 ns) and fall‑time (≤ 10 ns) specifications.
Best Practice: Use pre‑compliance simulation tools (IBIS models for transceivers) to validate signal integrity over the target cable length before PCB fabrication. This significantly reduces first‑pass failures during conformance testing.
Compliance and Conformance Testing
To claim conformance with IEC 14776-112-04, equipment must pass a suite of tests typically conducted by accredited laboratories (such as those following ISO/IEC 17025). The test regime includes:
- Electrical conformance: Measurement of driver output levels, receiver thresholds, and termination voltage at the worst‑case load.
- Timing conformance: Verification that all protocol timing parameters (e.g., REQ/ACK skew, data setup/hold) meet the limit values for the claimed speed (Fast‑20 or Fast‑40).
- Protocol conformance: Execution of a defined test sequence (e.g., bus free, selection, data transfer) to ensure proper state machine behaviour and error handling.
- Cable and connector quality: Measurement of impedance, attenuation, and near‑end crosstalk (NEXT) on the test fixture.
Common Compliance Pitfall: Using a termination regulator with insufficient decoupling can cause TERMPWR noise, leading to intermittent data errors. Always place at least 10 µF ceramic and 100 µF electrolytic capacitors within 1 cm of the terminator power pin.
Manufacturers should maintain a detailed compliance matrix mapping each clause of the standard to their design verification records. The Canadian adoption (CAN/CSA‑ISO/IEC 14776‑112‑04) includes minor national deviations, primarily concerning environmental stress testing. Designers targeting the Canadian market must verify these additional requirements.
Frequently Asked Questions
Q: What is the difference between SPI‑2 (IEC 14776‑112‑04) and earlier SCSI‑2 standards?
A: SPI‑2 introduces a more rigorous timing model for high-speed data transfer (Fast‑40), adds support for Low-Voltage Differential (LVD) signalling, and clarifies termination and cable requirements. It supersedes the earlier SCSI‑2 (SPI‑1) specifications for parallel interfaces.
A: SPI‑2 introduces a more rigorous timing model for high-speed data transfer (Fast‑40), adds support for Low-Voltage Differential (LVD) signalling, and clarifies termination and cable requirements. It supersedes the earlier SCSI‑2 (SPI‑1) specifications for parallel interfaces.
Q: Can I mix LVD and SE devices on the same SCSI bus?
A: Yes, if all devices support the LVD/SE handshake protocol defined in the standard. The bus defaults to SE operation when any SE-only device is detected. However, mixing HVD with either SE or LVD is not allowed without a converter.
A: Yes, if all devices support the LVD/SE handshake protocol defined in the standard. The bus defaults to SE operation when any SE-only device is detected. However, mixing HVD with either SE or LVD is not allowed without a converter.
Q: What is the maximum number of devices supported on a single SPI‑2 bus?
A: The standard supports up to 16 devices (including the initiator) when using wide arbitration (16‑bit data bus). Single‑ended configurations are typically limited to 8 devices due to signal loading, while LVD can reach the full 16 devices.
A: The standard supports up to 16 devices (including the initiator) when using wide arbitration (16‑bit data bus). Single‑ended configurations are typically limited to 8 devices due to signal loading, while LVD can reach the full 16 devices.
Q: How does the compliance testing for IEC 14776‑112‑04 differ from that of IEC 14776‑111?
A: IEC 14776‑112‑04 (SPI‑2) includes additional tests for LVD electrical characteristics, more stringent timing margins for Fast‑40, and verification of the LVD/SE negotiation protocol. Test fixtures and calibration procedures are updated accordingly.
A: IEC 14776‑112‑04 (SPI‑2) includes additional tests for LVD electrical characteristics, more stringent timing margins for Fast‑40, and verification of the LVD/SE negotiation protocol. Test fixtures and calibration procedures are updated accordingly.
— Published 2026 —