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IEC 10728‑95 (2018) – VMEbus Bridge Specification for Microprocessor Systems
Scope, technical requirements, implementation highlights and compliance notes for the international standard on multi‑crate VMEbus interconnection
Scope of IEC 10728‑95 (2018)
IEC 10728‑95 (originally published in 1995, reaffirmed and updated through 2018) defines the electrical, mechanical, and protocol requirements for a VMEbus bridge that interconnects two or more VMEbus sub‑systems (crates). The bridge allows a single system to extend beyond the normal backplane limits, enabling larger, multi‑crate configurations while maintaining full software transparency. The standard addresses:
- Functional partitioning between bridge devices across crates.
- Signal definitions, timing, and DC characteristics for the bridge interface.
- Bus arbitration and data transfer protocols across the bridge.
- Mechanical form factors for plug‑in bridge modules.
- Electromagnetic compatibility (EMC) limits derived from the IEC 61000 series.
Adoption of this standard ensures that VMEbus bridge units from different vendors are interoperable and can be integrated without custom glue logic. The 2018 revision brought clarifications on signal integrity for higher clock rates and updated EMC requirements.
Key benefit: Systems designed to IEC 10728‑95 (2018) can scale to dozens of crates while preserving the deterministic real‑time behaviour that VMEbus is known for.
Technical Requirements
Electrical Characteristics
The bridge interface must operate within the same voltage and noise margins as the base VMEbus specification (IEC 821‑1987 / IEEE 1014). All bridge signals are differential where possible to maintain noise immunity across long distances between crates. Table 1 summarises the critical electrical parameters.
| Parameter | Value | Condition |
|---|---|---|
| Supply voltage (Vcc) | +5 V ± 0.25 V | At bridge module pins |
| Input threshold low (VIL) | –0.5 V min, 0.8 V max | TTL levels for backplane signals |
| Input threshold high (VIH) | 2.0 V min | |
| Output low (VOL) | 0.4 V max (IOL = 32 mA) | |
| Output high (VOH) | 2.4 V min (IOH = –3 mA) | |
| Differential pair common‑mode range | ±7 V | Bridge‑to‑bridge link |
| Propagation delay (max) | 15 ns | Through bridge logic |
| Crosstalk attenuation | ≥ 40 dB | Between adjacent lines |
Table 1 – Key electrical parameters of the VMEbus bridge interface per IEC 10728‑95 (2018).
Protocol and Timing
The bridge implements a store‑and‑forward or cut‑through scheme, depending on the data width and transfer mode. The standard defines three bridge classes:
- Class A: Transparent address decoding; supports all VMEbus transfer modes (D16, D32, D64).
- Class B: Block transfer only; optimized for high‑throughput streaming.
- Class C: Multiplexed address/data for reduced pin count.
Arbitration across the bridge uses a distributed daisy‑chain mechanism identical to the backplane, with a bridge request level that ensures fairness among crates. The maximum allowed latency from request to grant is 256 bus clocks (at 20 MHz, i.e., 12.8 µs).
Common pitfall: When using Class A bridges with mixed‑width transfers, ensure that the bridge’s address decoding does not break PCI compatibility layers often added in VME systems.
Mechanical Form Factor
Bridge modules must adhere to the 6U height (233.35 mm) and 160 mm depth form‑factor defined by the VME64x mechanical profile (IEEE 1101.1). The front panel includes a 15‑pin high‑density D‑connector for external cabling between crates. The standard also specifies a 3U variant (100 mm height) for compact systems.
Implementation Highlights
Successful implementation of an IEC 10728‑95 (2018) compliant bridge requires attention to:
- Signal integrity: Controlled impedance (65 Ω ± 10 % for differential traces) and minimal stub lengths on the inter‑crate cable.
- Clock distribution: A global synchronous clock (20 MHz) must be provided to all crates, with less than 2 ns skew between bridge devices.
- Power sequencing: The bridge must survive hot‑swap events without introducing glitches on the backplane bus.
- Configuration ROM: An I²C EEPROM containing bridge parameters (vendor ID, class, allowed transfer modes) simplifies system enumeration.
Implementation tip: Use an FPGA‑based bridge core (e.g., with a hardened PCIe or serial interface) to reduce part count and simplify compliance testing. Many commercial offerings now integrate the IEC 10728 protocol stack into a single device.
Compliance and Testing
Conformance to IEC 10728‑95 (2018) is verified through a suite of tests defined in Annex A (normative). The test procedure covers:
- Electrical tests: Thresholds, output drive, propagation delays, and noise margin.
- Protocol tests: Arbitration fairness, burst handling, and error recovery (bus time‑out).
- EMC tests: Radiated and conducted emissions according to IEC 61000‑6‑4, and immunity per IEC 61000‑6‑2.
- Interoperability tests: Plug‑fest exercises with at least three different bridge vendors to confirm transparent data transfer across six crates.
IECEE (IEC System of Conformity Assessment Schemes) offers a certification framework for bridge modules. Only products that pass all mandatory tests may carry the IECEE CB mark, which is widely accepted in procurement contracts for industrial and military systems.
Non‑compliance risk: Using a non‑compliant bridge in a multi‑vender system can cause sporadic data corruption, bus hangs, and complete system crashes. In safety‑critical applications (e.g., railway signalling), this can lead to certification failure and costly redesign.
Frequently Asked Questions
Q: Is IEC 10728‑95 (2018) still relevant for modern VME systems?
A: Yes. While many new designs use serial backplanes, large installed bases in aerospace, defence, and nuclear research rely on VMEbus. The 2018 revision ensures that bridge modules can handle increased data widths (D64) and maintain compatibility with legacy equipment.
A: Yes. While many new designs use serial backplanes, large installed bases in aerospace, defence, and nuclear research rely on VMEbus. The 2018 revision ensures that bridge modules can handle increased data widths (D64) and maintain compatibility with legacy equipment.
Q: Can I use a commercial off‑the‑shelf PCIe‑to‑VME bridge and claim compliance?
A: Not automatically. The bridge must implement the full protocol stack specified by IEC 10728, including arbitration, error recovery, and timing constraints. Many PCI bridge chips hide details that violate the standard. Always check the manufacturer’s conformance report.
A: Not automatically. The bridge must implement the full protocol stack specified by IEC 10728, including arbitration, error recovery, and timing constraints. Many PCI bridge chips hide details that violate the standard. Always check the manufacturer’s conformance report.
Q: Does the standard cover cabling between crates?
A: It provides guidelines for cable type (shielded twisted‑pair, Belden 1800F or equivalent), maximum length (25 m), and termination. Specific cable ratings must be chosen per the installation environment, but the electrical interface is fully defined.
A: It provides guidelines for cable type (shielded twisted‑pair, Belden 1800F or equivalent), maximum length (25 m), and termination. Specific cable ratings must be chosen per the installation environment, but the electrical interface is fully defined.
Q: Is there a role for this standard in VPX or CompactPCI systems?
A: Not directly, but the bridge concepts—especially for multi‑crate synchronisation and transparent address mapping—influenced similar extensions in VPX (OpenVPX). The arbitration and timing models remain useful reference material.
A: Not directly, but the bridge concepts—especially for multi‑crate synchronisation and transparent address mapping—influenced similar extensions in VPX (OpenVPX). The arbitration and timing models remain useful reference material.
— IEC 10728‑95 (2018) Technical Overview, 2026 —