IEC 60191: Semiconductor Package Mechanical Standards — The Physical Foundation of SMT Automation

Semiconductor Package Standards: Why IC Dimensions Must Be Precise to Microns

IEC 60191-2 specifies mechanical standardization of semiconductor devices — the package outline dimensions, lead pitch, and coplanarity requirements. This is the physical foundation enabling SMT pick-and-place machines to achieve high-speed automated assembly.

Core requirements: (1) Lead coplanarity — all lead bottoms must lie within the same plane, deviation ≤0.1 mm (for QFP and SOIC packages). A single lead lifted 0.15 mm will not contact the solder paste during reflow — guaranteed 100% dry joint. (2) Package body tolerance — pick-and-place nozzles locate by package outline; dimensional deviation exceeding ±0.2 mm causes pickup failure or placement offset. (3) Lead pitch — from 2.54 mm (DIP) to 0.3 mm (BGA), finer pitch demands correspondingly higher PCB fabrication precision.

TN Lab — Without IEC 60191 package standardization, the automated mass production of modern electronics would not exist.